Orthogonal differential vector signaling codes with embedded clock

Patent metadata

Field	Value
Publication number	US-10122561-B2
Application number	US-201715829904-A
Country	US
Kind code	B2
Filing date	Dec 2, 2017
Priority date	Aug 1, 2014
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

First claim

We claim:

1. A method comprising:
receiving, at a plurality of multi-input comparators (MICs), a set of symbols of a codeword of a vector signaling code via wires of a multi-wire bus;
generating a plurality of sub-channel data signals at a first subset of MICs of the plurality of MICs, each sub-channel data signal generated by a respective MIC of the first subset, the respective MIC applying a respective set of data input coefficients to the set of symbols of the codeword, the respective set of data input coefficients selected according to a respective row of a plurality of rows of an orthogonal matrix; and
receiving first and second subsets of symbols of the set of the symbols of the codeword of the vector signaling code at a timing MIC of the plurality of MICs, the first and second subsets of the symbols received via first and second subsets of wires of the multi-wire bus, respectively;
responsively generating, using the timing MIC, a sub-channel clock signal by applying a set of timing input coefficients to the first and second subsets of symbols of the set symbols to detect changes in common mode across the first subset of wires with respect to common mode across the second subset of wires, the changes in common mode associated with transitions in the sub-channel clock signal.

2. The method of claim 1 , further comprising sampling the plurality of sub-channel data signals according to the sub-channel clock signal.

3. The method of claim 1 , wherein the sub-channel clock signal has a ½ unit interval delay with respect to the plurality of sub-channel data signals.

4. The method of claim 1 , wherein each MIC of the plurality of MICs is connected to all wires of the multi-wire bus.

5. The method of claim 1 , wherein one or more MICs of the first subset of MICs is connected to a portion of wires of the multi-wire bus.

6. The method of claim 1 , wherein the symbols of the codeword of the vector signaling code have symbol values selected from at least a ternary alphabet.

7. The method of claim 1 , wherein the at least a ternary alphabet is a quaternary alphabet comprising a set of symbol values ±1, ±⅓.

8. The method of claim 1 , wherein the set of timing input coefficients comprises coefficients having an equal magnitude.

9. The method of claim 1 , wherein the set of data input coefficients and timing input coefficients are distinct, orthogonal permutations of a vector [+1 +1 −1 −1].

10. The method of claim 9 , wherein the vector signaling code is an Ensemble Non-Return-to-Zero (ENRZ) code.

11. An apparatus comprising:
a plurality of data multi-input comparators (MICs) configured to receive a set of symbols of a codeword of a vector signaling code via wires of a multi-wire bus, the plurality of data MICs configured to generate a plurality of sub-channel data signals, each sub-channel data signal generated by a respective data MIC of the plurality of data MICs, the respective data MIC applying a respective set of data input coefficients to the set of symbols of the codeword, the respective set of data input coefficients selected according to a respective row of a plurality of rows of an orthogonal matrix; and
a timing MIC configured to receive first and second subsets of symbols of the set of the symbols of the codeword of the vector signaling code, the first and second subsets of the symbols received via first and second subsets of wires, respectively, the timing MIC further configured to responsively generate a sub-channel clock signal by applying a set of timing input coefficients to the first and second subsets of symbols of the set symbols to detect changes in common mode across the first subset of wires with respect to common mode across the second subset of wires, the changes in common mode associated with transitions in the sub-channel clock signal.

12. The apparatus of claim 11 , further comprising a plurality of samplers configured to sample the plurality of sub-channel data signals according to the sub-channel clock signal.

13. The apparatus of claim 11 , wherein the sub-channel clock signal has a ½ unit interval delay with respect to the plurality of sub-channel data signals.

14. The apparatus of claim 11 , wherein the plurality of data MICs and the timing MIC are connected to all wires of the multi-wire bus.

15. The apparatus of claim 11 , wherein one or more of the data MICs is connected to a portion of wires of the multi-wire bus.

16. The apparatus of claim 11 , wherein the symbols of the codeword of the vector signaling code have symbol values selected from at least a ternary alphabet.

17. The apparatus of claim 11 , wherein the at least a ternary alphabet is a quaternary alphabet comprising a set of symbol values ±1, ±⅓.

18. The apparatus of claim 11 , wherein the set of timing input coefficients comprises coefficients having an equal magnitude.

19. The apparatus of claim 11 , wherein the set of data input coefficients and timing input coefficients are distinct, orthogonal permutations of a vector [+1 +1 −1 −1].

20. The apparatus of claim 19 , wherein the vector signaling code is an Ensemble Non-Return-to-Zero (ENRZ) code.

Assignees

• Kandou Labs SA

Inventors

• Holden Brian
• Shokrollahi Amin

Classifications

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• Y02D10/151

  Cross-Sectional Technologies · mapped topic

• G11C7/1093

  Input synchronization · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title