Phase detector in a delay locked loop

Patent metadata

Field	Value
Publication number	US-10122526-B2
Application number	US-201715477078-A
Country	US
Kind code	B2
Filing date	Apr 1, 2017
Priority date	Apr 1, 2017
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

First claim

What is claimed is:

1. A phase detector comprising:
a reference clock;
a feedback clock;
a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock;
a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state; and
a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

2. The phase detector of claim 1 , wherein the lead-lag status indicates that the feedback clock leads the reference clock or that the feedback clock lags the reference clock.

3. The phase detector of claim 1 , wherein the second latch loads the lead-lag status in accordance with a defined time delay.

4. The phase detector of claim 1 , wherein:
the lead-lag status indicates that the feedback clock lags the reference clock, and:
the first latch output (q0/q0b) of the first latch is set to a low state when the reference clock produces clock signals transiting from a low state to high state;
a second latch output (q1/q1b) of the second latch is set to a low state when the reference clock and the feedback clock are both in high states; and
a third latch output (q2/q2b) of the third latch is set to a low state when the reference clock and the feedback clock produce clock signals in low states.

5. The phase detector of claim 4 , wherein the phase detector is configured to send a down output value of ‘1’ to a delay locked loop (DLL) state machine to decrease a delay chain delay when the third latch output (q2/q2b) is set to the low state.

6. The phase detector of claim 1 , wherein:
the lead-lag status indicates that the feedback clock leads the reference clock, and:
the first latch output (q0/q0b) of the first latch is set to a high state when the feedback clock produces clock signals transiting from a low state to high state;
a second latch output (q1/q1b) of the second latch is set to a high state when the reference clock and the feedback clock are both in high states; and
a third latch output (q2/q2b) of the third latch is set to a high state when the reference clock and the feedback clock produce clock signals in low states.

7. The phase detector of claim 6 , wherein the phase detector is configured to send an up output value of ‘1’ to a DLL state machine to increase a delay chain delay when the third latch output (q2/q2b) is set to the high state.

8. The phase detector of claim 1 , wherein a first signal load (load0) in the first latch becomes a self-timed high pulse when the reference clock and the feedback clock are high.

9. The phase detector of claim 1 , wherein a first signal load (load0) in the second latch and a second signal load (load1) in the third latch do not transit to a high state when the reference clock and the feedback clock are 180 degrees out-of-phase, and the second latch and the third latch are isolated from updates to prevent incorrect toggling.

10. The phase detector of claim 1 , wherein the first latch, the second latch and the third latch are cross coupled latches.

11. The phase detector of claim 1 , wherein the phase detector is included in a digital delay locked loop (DLL).

12. An apparatus comprising:
a reference clock;
a feedback clock;
a first cross coupled latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock, wherein the lead-lag status indicates that the feedback clock leads the reference clock or that the feedback clock lags the reference clock;
a second cross coupled latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state; and
a third cross coupled latch that loads the lead-lag status from the second cross coupled latch to the third cross coupled latch when the reference clock and the feedback clock produce clock signals in a low state.

13. The apparatus of claim 12 , wherein:
the lead-lag status indicates that the feedback clock lags the reference clock, and:
the first latch output (q0/q0b) of the first cross coupled latch is set to a low state when the reference clock produces clock signals transiting from a low state to high state;
a second latch output (q1/q1b) of the second cross coupled latch is set to a low state when the reference clock and the feedback clock are both in high states, wherein a first signal load (load0) in the first cross coupled latch loads the low state of the first latch output (q0/q0b) into the second cross coupled latch; and
a third latch output (q2/q2b) of the third cross coupled latch is set to a low state when the reference clock and the feedback clock produce clock signals in low states, wherein a second signal load (load1) in the second cross coupled latch loads the low state of the second latch output (q1/q1b) into the third cross coupled latch,
wherein the phase detector is configured to send a down output value of ‘1’ to a delay locked loop (DLL) state machine to decrease a delay chain delay when the third latch output (q2/q2b) is set to the low state.

14. The apparatus of claim 12 , wherein:
the lead-lag status indicates that the feedback clock leads the reference clock, and:
the first latch output (q0/q0b) of the first cross coupled latch is set to a high state when the feedback clock produces clock signals transiting from a low state to high state;
a second latch output (q1/q1b) of the second cross coupled latch is set to a high state when the reference clock and the feedback clock are both in high states, wherein a first signal load (load0) in the first cross coupled latch loads the high state of the first latch output (q0/q0b) into the second cross coupled latch; and
a third latch output (q2/q2b) of the third cross coupled latch is set to a high state when the reference clock and the feedback clock produces clock signals in low states, wherein a second signal load (load1) in the second cross coupled latch loads the high state of the second latch output (q1/q1b) into the third cross coupled latch,
wherein the phase detector is configured to send an up output value of ‘1’ to a delay locked loop (DLL) state machine to increase a delay chain delay when the third latch output (q2/q2b) is set to the high state.

15. The apparatus of claim 12 , wherein a first signal load (load0) in the first cross coupled latch becomes a self-timed high pulse when the reference clock and the feedback clock are high.

16. The apparatus of claim 12 , wherein a first signal load (load0) in the second cross coupled latch and a second signal load (load1) in the third cross coupled latch do not transit to a high state when the reference clock and the feedback clock are 180 degrees out-of-phase, and the second cross coupled latch and the third cross coupled latch are isolated from updates to prevent incorrect toggling.

17. The apparatus of claim 12 , wherein the apparatus is a digital phase detector in a delay locked loop (DLL).

18. A method for performing phase detection, the method comprising:
setting, in a first latch of a phase detector, a first latch output depending on a lead-lag status between a reference clock and a feedback clock in the phase detector;
loading, in a second latch of the phase detector, the lead-lag status when the reference clock and the feedback clock produce clock signals in high states; and
loading, in a third latch of the phase detector, the lead-lag status from the second latch when the reference clock and the

Assignees

• Intel Corp

Inventors

• Wei Fangxing
• Shi Dan
• Allen Michael J

Classifications

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L7/04

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H04L7/0037

  Delay of clock signal · CPC title

• H04L7/027

  extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit · CPC title