Polar receiver system and method for Bluetooth communications

Patent metadata

Field	Value
Publication number	US-10122397-B2
Application number	US-201715655676-A
Country	US
Kind code	B2
Filing date	Jul 20, 2017
Priority date	Mar 28, 2017
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Circuitry and methods are described for digital signal demodulation. In a configurable receiver, a method includes receiving a radio frequency signal at the configurable receiver, operating the configurable receiver in a first mode, the first mode including providing the radio frequency signal to an amplitude detection circuit to determine an amplitude, providing the radio frequency signal to a phase detection circuit to determine a phase, and providing the amplitude and phase to a coordinate rotation digital computer (CORDIC) logic circuit, and operating the configurable receiver in a low power mode upon receiving an indication to selectively disable the amplitude detection circuit, the low power mode including providing the radio frequency signal to the phase detection circuit to determine the phase, and providing the phase and a predetermined constant value in lieu of the amplitude to the CORDIC logic circuit.

First claim

The invention claimed is:

1. A configurable receiver comprising:
a frequency division circuit to receive a radio frequency signal and generate a frequency-divided output signal;
a time-to-digital converter coupled to the frequency division circuit to identify a period of the frequency-divided output signal;
a digital subtractor coupled to the time-to-digital converter to generate an offset digital time signal, the offset digital time signal operable to identify a shift in phase of the frequency-divided output signal by identifying a temporary change in the period of the frequency-divided output signal;
a digital integrator coupled to the digital subtractor to provide a value representing a phase of the radio frequency signal;
an amplitude detection circuit coupled to the frequency division circuit, the amplitude detection circuit coupled to receive the radio frequency signal and generate the amplitude signal; and
a mode control circuit coupled to the amplitude detection circuit and to an input of a coordinate rotation digital computer (CORDIC) logic circuit, the mode control circuit configured to receive an indication to selectively disable the amplitude detection circuit and to provide a predetermined constant value to the CORDIC logic circuit.

2. The configurable receiver of claim 1 , wherein the CORDIC logic circuit is coupled to the digital integrator and coupled to receive the amplitude signal, the CORDIC logic circuit to generate in-phase (I) and quadrature (Q) components of the radio frequency signal.

3. The configurable receiver of claim 2 , further comprising:
a low pass filter coupled to the CORDIC logic circuit; and
a second CORDIC logic circuit coupled to receive the filtered I and Q components of the radio frequency signal from the low pass filter and provide a baseband phase signal.

4. The configurable receiver of claim 1 , further comprising a register operable to sample the value representing the phase of the radio frequency signal and provide a sampled signal to the CORDIC logic circuit.

5. The configurable receiver of claim 1 wherein the amplitude detection circuit comprises:
an envelope detector coupled to receive the radio frequency signal and detect an amplitude of the radio frequency signal;
an analog-to-digital circuit coupled to the envelope detector; and
alignment logic coupled to the analog-to-digital circuit, the alignment logic configured to provide temporal alignment between the amplitude of the radio frequency signal and the phase a of the radio frequency signal.

6. The configurable receiver of claim 1 wherein the indication to selectively disable the amplitude detection circuit is a Bluetooth low energy (BLE) indication to provide a constant value of 1 as the amplitude signal.

7. A method for a configurable receiver comprising:
receiving a radio frequency signal at the configurable receiver;
operating the configurable receiver in a first mode, the first mode including:
providing the radio frequency signal to an amplitude detection circuit to determine an amplitude;
providing the radio frequency signal to a phase detection circuit to determine a phase; and
providing the amplitude and phase to a coordinate rotation digital computer (CORDIC) logic circuit; and

operating the configurable receiver in a low power mode upon receiving an indication to selectively disable the amplitude detection circuit, the low power mode including:
providing the radio frequency signal to the phase detection circuit to determine the phase; and
providing the phase and a predetermined constant value in lieu of the amplitude to the CORDIC logic circuit.

8. The method of claim 7 wherein the operating the configurable receiver in the low power mode upon receiving the indication further comprises:
receiving the indication to selectively disable the amplitude detection circuit at a mode control circuit, the mode control circuit coupled to the amplitude detection circuit and to an input of the (CORDIC) logic circuit, the indication to selectively disable the amplitude detection circuit and to provide the predetermined constant value to the CORDIC logic circuit.

9. The method of claim 7 wherein the low power mode is a Bluetooth low energy (BLE) mode.

10. The method of claim 7 wherein the predetermined constant value is “1”.

11. The method of claim 7 further comprising:
filtering an output of the CORDIC logic circuit to generate filtered in-phase (I) and quadrature (Q) components of the radio frequency signal; and
providing the filtered I and Q components of the radio frequency signal to a second CORDIC logic circuit to generate a baseband phase signal.

12. The method of claim 7 wherein providing the radio frequency signal to the phase detection circuit to determine the phase further comprises:
dividing the radio frequency signal to generate a frequency-divided output signal;
identifying a period of the frequency-divided output signal;
generating an offset digital time signal to identify a shift in phase of the frequency-divided output signal by identifying a temporary change in the period; and
integrating the offset digital time signal to provide a value representing a phase of the radio frequency signal.

13. The method of claim 7 further comprising:
operating the configurable receiver in the low power mode as a function of a determination that the radio frequency signal is a constant envelope modulated signal.

14. The method of claim 7 wherein the radio frequency signal is one or more of a phase shift keying (PSK) signal, a quadrature amplitude modulation (QAM) signal, a frequency shift keying (FSK) signal, a binary frequency-shift keying (BFSK) signal, a multiple frequency-shift keying (MFSK) signal and a minimum-shift keying (MSK) signal.

15. A system comprising:
a processing device;
a memory coupled to the processing device; and
a configurable receiver coupled to the processing device, the configurable receiver including:
a frequency division circuit to receive a radio frequency signal and generate a frequency-divided output signal;
a time-to-digital converter coupled to the frequency division circuit to identify a period of the frequency-divided output signal;
a digital subtractor coupled to the time-to-digital converter to generate an offset digital time signal, the offset digital time signal operable to identify a shift in phase of the frequency-divided output signal by identifying a temporary change in the period of the frequency-divided output signal;
a digital integrator coupled to the digital subtractor to provide a value representing a phase of the radio frequency signal;
an amplitude detection circuit coupled to the frequency division circuit, the amplitude detection circuit coupled to receive the radio frequency signal and generate the amplitude signal; and
a mode control circuit coupled to the amplitude detection circuit and to an input of a coordinate rotation digital computer (CORDIC) logic circuit, the mode control circuit configured to receive an indication to selectively disable the amplitude detection circuit and to provide a predetermined constant value to the CORDIC logic circuit.

16. The system of claim 15 , wherein the CORDIC logic circuit is coupled to the digital integrator and coupled to receive the amplitude signal, the CORDIC logic circuit to generate in-phase (I) and quadrature (Q) components of the radio frequency signal.

17. The system of claim 16 , further comprising:
a low pass filter coupled to the CORDIC logic circuit; and
a second CORDIC logic circuit coupled to receive the filt

Assignees

• Innophase Inc

Inventors

• Xu Yang
• Munoz Hermoso Sara

Classifications

• H04J1/02

  Details · CPC title

• H04L27/3845

  using non - coherent demodulation, i.e. not using a phase synchronous carrier · CPC title

• H04L27/00

  Modulated-carrier systems · CPC title

• H04W4/80

  Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication · CPC title

• H04L27/38

  Demodulator circuits; Receiver circuits · CPC title