Logical interleaver

Patent metadata

Field	Value
Publication number	US-10122384-B2
Application number	US-201615157814-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	May 18, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.

First claim

What is claimed is:

1. A memory device, comprising:
a first interleaving circuit coupled to read and write ports, wherein the first interleaving circuit:
receives data words from one or more of the read and write ports,
physically interleaves the received data words, and
generates a first error correction code based on the physical interleaving of the received data words; and

a second interleaving circuit that is separate from and coupled to the first interleaving circuit, wherein the second interleaving circuit:
receives the data words from the first interleaving circuit,
logically interleaves the data words received from the first interleaving circuit, and
generates a second error correction code based on the logical interleaving of the data words received from the first interleaving circuit as a complement to the first error correction code by interleaving data bits from multiple different data words and storing modified data words based on the multiple different data words,

wherein the physical interleaving of the first interleaving circuit and the logical interleaving of the second interleaving circuit protect data stored in the memory device against multi-cell upset.

2. The device of claim 1 , wherein each of the data bits comprises a single unit of data, and wherein each of the multiple different data words comprises a plurality of data bits.

3. The device of claim 1 , wherein the data words include the multiple different data words, and wherein each of the multiple different data words comprises a plurality of data bits.

4. The device of claim 1 , wherein the first interleaving circuit comprises an error correction code (ECC) circuit that generates the first error correction code.

5. The device of claim 1 , further comprising a checksum generating circuit that generates hash data from at least a portion of the received data words, wherein the first interleaving circuit and the second interleaving circuit are coupled to the checksum generating circuit, and wherein the first interleaving circuit and the second interleaving circuit receive the hash data from the checksum generating circuit so as to detect errors introduced to the received data words during transmission.

6. The device of claim 1 , further comprising a memory circuit that stores one or more of the first error correction code, the second error correction code, and the modified data words.

7. The device of claim 6 , wherein the memory circuit comprises a static random access memory (SRAM) circuit.

8. The device of claim 6 , wherein the first interleaving circuit is coupled to the memory circuit, and wherein the first interleaving circuit stores the first error correction code in the memory circuit.

9. The device of claim 6 , wherein the second interleaving circuit is coupled to the memory circuit, and wherein the second interleaving circuit stores the second error correction code and the modified data words in the memory circuit.

10. The device of claim 1 , wherein the second interleaving circuit interleaves data bits from the multiple different data words by switching one or more data bit values of a first data word with one or more data bit values of a second data word that are different than the first data word.

11. The device of claim 1 , wherein the second interleaving circuit interleaves data bits from the multiple different data words by switching one or more data bit values of a first set of data words with one or more data bit values of a second set of data words that are different than the first set of data words.

12. The device of claim 1 , wherein the second interleaving circuit interleaves data bits from the multiple different data words by shifting placement of one or more data bit values of a first data word with one or more data bit values of a second data word that are different than the first data word.

13. The device of claim 1 , wherein the second interleaving circuit interleaves data bits from the multiple different data words by shifting placement of one or more data bit values of a first set of data words with one or more data bit values of a second set of data words that are different than the first set of data words.

14. A memory circuit, comprising:
a first interleaving circuit coupled to read and write ports, wherein the first interleaving circuit:
receives binary coded words from one or more of the read and write ports,
physically interleaves the received binary coded words, and
generates a first error correction code based on the physical interleaving of the received binary coded words; and

a second interleaving circuit that is separate from and coupled to the first interleaving circuit, wherein the second interleaving circuit:
receives the binary coded words from the first interleaving circuit,
logically interleaves the binary coded words received from the first interleaving circuit,
generates a second error correction code based on the logical interleaving of the received binary coded words as a complement to the first error correction code, and
stores modified binary coded words based on interleaved data bits from multiple different binary coded words,

wherein the physical interleaving of the first interleaving circuit and the logical interleaving of the second interleaving circuit protect data stored in the memory circuit against multi-cell upset.

15. The circuit of claim 14 , further comprising a checksum generator that generates hash data from at least a portion of the received binary coded words, wherein the first interleaving circuit and the second interleaving circuit are coupled to the checksum generator, and wherein the first interleaving circuit and the second interleaving circuit receive the hash data from the checksum generator so as to detect errors introduced to the received binary coded words during transmission.

16. The circuit of claim 14 , wherein the second interleaving circuit interleaves data bits from multiple different binary coded words by switching one or more data bit values of a first binary coded word with one or more values of a second binary coded word that are different than the first binary coded word.

17. The circuit of claim 14 , wherein the second interleaving circuit interleaves data bits from multiple different binary coded words by shifting placement of one or more data bit values of a first binary coded word with one or more values of a second binary coded word that are different than the first binary coded word.

18. A method for reducing memory storage errors, the method comprising:
receiving data words from one or more read and write ports with a first interleaver circuit that is coupled to the one or more read and write ports, the first interleaver circuit physically interleaving the received data words;
receiving the data words from the first interleaver circuit with a second interleaver circuit that is coupled to the first interleaver circuit, the second interleaver circuit logically interleaving the data words received from the first interleaver circuit;
generating a first error correction code with the first interleaver circuit based on the physical interleaving of the received data words;
generating a second error correction code with the second interleaver circuit based on the logical interleaving of the received data words as a complement to the first error correction code by interleaving data bits from multiple different data words and storing modified data words based on the multiple different data words,
wherein the second interleaver circuit is separate from the first interleaver circ

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lai Liangzhen
• Chandra Vikas
• Carpenter Gary Dale

Classifications

• H03M13/2792

  Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing · CPC title

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• H03M13/05 Primary

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• H03M13/27

  using interleaving techniques · CPC title