Interference-immunized multiplexer

Patent metadata

Field	Value
Publication number	US-10122348-B2
Application number	US-201615084918-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.

First claim

What is claimed is:

1. A multiplexer comprising:
a first buffer comprising:
a first selection input configured to receive a first selection signal;
a first logical input configured to receive a first logical input signal;
a first logical output; and
a first ground;

a second buffer comprising:
a second selection input configured to receive a second selection signal;
a second logical input configured to receive a second logical input signal;
a second logical output; and
a second ground; and

an output circuit comprising:
a third logical input coupled to the first logical output; and
a fourth logical input coupled to the second logical output independently of the first logical output,

wherein the multiplexer is configured to:
couple, when the first selection signal has a first value, the first logical input to the third logical input to produce the first logical input signal to the third logical input; and
couple, when the first selection signal has a second value, the first logical input to the first ground.

2. The multiplexer of claim 1 , wherein the first selection input comprises a third selection input and a fourth selection input, wherein the first logical input is a differential first logical input comprising a fifth logical input and a sixth logical input, and wherein the first logical output is a differential first logical output comprising a third logical output and a fourth logical output.

3. The multiplexer of claim 2 , wherein the first buffer further comprises:
a voltage source;
a first transistor coupled to the voltage source and the third selection input;
a second transistor coupled to the fourth selection input and the first ground;
a third transistor coupled to the fourth selection input, the first ground, and the fourth logical output; and
a fourth transistor coupled to the fourth selection input, the first ground, and the third logical output.

4. The multiplexer of claim 3 , wherein the first transistor is a p-type metal-oxide-semiconductor (PMOS) transistor, and wherein the second transistor, the third transistor, and the fourth transistor are n-type metal-oxide-semiconductors (NMOSs).

5. The multiplexer of claim 1 , wherein the multiplexer is further configured to:
couple, when the second selection signal has the first value, the second logical input to the fourth logical input to produce the second logical input signal to the fourth logical input; and
couple, when the second selection signal has the second value, the second logical input to the second ground.

6. The multiplexer of claim 1 , wherein the first ground and the second ground are the same.

7. The multiplexer of claim 1 , wherein the output circuit comprises a multiplexer output, and wherein the multiplexer output is a differential multiplexer output comprising a first multiplexer output and a second multiplexer output.

8. The multiplexer of claim 7 , wherein the output circuit further comprises:
a fifth logical input;
a sixth logical input;
a current source; and
a third ground coupled to the current source.

9. The multiplexer of claim 8 , wherein the output circuit further comprises:
a first transistor directly coupled to the first multiplexer output and the current source;
a second transistor directly coupled to the second multiplexer output and the current source;
a third transistor directly coupled to the first multiplexer output and the current source; and
a fourth transistor directly coupled to the second multiplexer output and the current source.

10. The multiplexer of claim 9 , wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are n-type metal-oxide-semiconductor (NMOS) transistors.

11. A method implemented in a multiplexer, the method comprising:
receiving, by a first selection input of a first buffer, a first selection signal;
receiving, by a second selection input of a second buffer, a second selection signal;
receiving, by a first logical input of the first buffer, a first logical input signal;
receiving, by a second logical input of the second buffer, a second logical input signal;
coupling, by the multiplexer and when the first selection signal has a first value, the first logical input to a third logical input of an output circuit to produce the first logical input signal to the third logical input;
coupling, by the multiplexer and when the first selection signal has a second value, the first logical input to a first ground of the first buffer;
coupling, by the multiplexer and when the second selection signal has the first value, the second logical input to a fourth logical input of the output circuit to produce the second logical input signal to the fourth logical input; and
coupling, by the multiplexer and when the second selection signal has the second value, the second logical input to a second ground of the second buffer.

12. The method of claim 11 , wherein the first ground and the second ground are the same.

13. The method of claim 11 , wherein the first selection input comprises a third selection input and a fourth selection input, and wherein the first logical input is a differential first logical input comprising a fifth logical input and a sixth logical input.

14. The method of claim 11 , wherein the output circuit comprises a multiplexer output, and wherein the multiplexer output is a differential multiplexer output comprising a first multiplexer output and a second multiplexer output.

Assignees

• Futurewei Technologies Inc

Inventors

• Gu Liang
• Cao Yuming
• Lei Gong
• Dang Yen
• Gu Yifan
• Lee Hungyi
• Deshpande Mamatha
• Shih Shou-Po
• Duan Yan

Classifications

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H04J3/047

  Distributors with transistors or integrated circuits · CPC title

• H03K17/6257

  with several inputs only combined with selecting means · CPC title

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title