Co-integrated bulk acoustic wave resonators

Patent metadata

Field	Value
Publication number	US-10122345-B2
Application number	US-201414392126-A
Country	US
Kind code	B2
Filing date	Jun 26, 2014
Priority date	Jun 26, 2013
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

An electrical circuit assembly can include a semiconductor integrated circuit, such as fabricated including CMOS devices. A first lateral-mode resonator can be fabricated upon a surface of the semiconductor integrated circuit, such as including a deposited acoustic energy storage layer including a semiconductor material, a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer, and a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit. The semiconductor integrated circuit can include one or more transistor structures, such as fabricated prior to fabrication of the lateral-mode resonator. Fabrication of the lateral-mode resonator can include low-temperature processing specified to avoid disrupting operational characteristics of the transistor structures.

First claim

The claimed invention is:

1. An electrical circuit assembly, comprising:
a semiconductor integrated circuit; and
a first lateral-mode resonator fabricated upon a surface of the semiconductor integrated circuit, the first lateral-mode resonator comprising:
a deposited acoustic energy storage layer comprising a semiconductor layer;
a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer;
a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit; and
an acoustic mirror located between the deposited acoustic energy storage layer and the semiconductor integrated circuit;
wherein the semiconductor integrated circuit includes one or more transistor structures.

2. The electrical circuit assembly of claim 1 , wherein the semiconductor integrated circuit comprises complementary metal-oxide-semiconductor (CMOS) devices.

3. The electrical circuit assembly of claim 1 , wherein the semiconductor layer of the deposited acoustic storage layer comprises a silicon layer.

4. The electrical circuit assembly of claim 1 , comprising:
a dielectric region located upon a surface of the semiconductor integrated circuit, the dielectric region coupled to the deposited acoustic energy storage layer and defining a cavity between the deposited acoustic energy storage layer and the semiconductor integrated circuit;
wherein the acoustic energy storage layer includes a released configuration suspended from the dielectric region.

5. The electrical circuit assembly of claim 1 , comprising a second lateral-mode resonator fabricated upon the semiconductor integrated circuit and electrically coupled to the semiconductor integrated circuit, the second lateral-mode resonator having one or more lateral dimensions that are different from the first lateral-mode resonator.

6. The electrical circuit assembly of claim 1 , comprising the first lateral-mode resonator being included in an array of lateral-mode resonators fabricated upon the semiconductor integrated circuit;
wherein at least some of the lateral-mode resonators are coupled to the semiconductor integrated circuit or to one another.

7. The electrical circuit assembly of claim 6 , wherein the semiconductor integrated circuit includes a transistor-based switch circuit configured to establish a signal path including a selected one or more of the lateral-mode resonators included in the array.

8. The electrical circuit assembly of claim 6 , wherein the semiconductor integrated circuit includes a transistor-based switch circuit configured to select amongst two or more filter circuits, the filter circuits including a specified one or more of the lateral-mode resonators included in the array.

9. The electrical circuit assembly of claim 1 , comprising a second resonator having a structure and impedance different from the first lateral-mode resonator.

10. The electrical circuit assembly of claim 9 , wherein the second resonator comprises a bulk acoustic wave resonator fabricated upon the semiconductor integrated circuit and electrically coupled to one or more of the first lateral-mode resonator or the semiconductor integrated circuit.

11. The electrical circuit assembly of claim 1 , wherein the first lateral-mode resonator is electrically coupled to the semiconductor integrated circuit without requiring use of a wire bond; and
wherein the first lateral-mode resonator and semiconductor integrated circuit share a common semiconductor substrate.

12. The electrical circuit assembly of claim 11 , wherein the first lateral-mode resonator is electrically-coupled to the semiconductor integrated circuit using a via structure included as a portion of the first lateral-mode resonator coupled to a pad on the semiconductor integrated circuit.

13. The electrical circuit assembly of claim 1 , wherein the deposited piezoelectric layer comprises ZnO; and
wherein the semiconductor material of the deposited acoustic energy storage layer comprises one of a polycrystalline silicon layer or a silicon carbide layer.

14. The electrical circuit assembly of claim 1 , wherein the semiconductor layer of the deposited acoustic energy storage layer comprises silicon carbide.

15. An electrical circuit assembly, comprising:
a semiconductor integrated circuit including complementary metal-oxide-semiconductor (CMOS) transistor structures; and
an array of lateral-mode resonators fabricated upon the semiconductor integrated circuit, including a first lateral-mode resonator fabricated upon a surface of the semiconductor integrated circuit, the first lateral-mode resonator comprising:
a deposited acoustic energy storage layer comprising a semiconductor layer;
a deposited piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer;
a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to at least one of the transistor structures of the semiconductor integrated circuit; and
an acoustic mirror located between the deposited acoustic energy storage layer and the semiconductor integrated circuit.

16. The electrical circuit assembly of claim 15 , comprising:
a dielectric region located upon a surface of the semiconductor integrated circuit, the dielectric region coupled to the deposited acoustic energy storage layer and defining a cavity between the deposited acoustic energy storage layer and the semiconductor integrated circuit;
wherein the acoustic energy storage layer includes a released configuration suspended from the dielectric region.

17. A method, comprising:
forming an acoustic energy storage layer upon a surface of a semiconductor integrated circuit using a low-temperature deposition technique, the low-temperature deposition technique including a maximum temperature specified not to disrupt operating characteristics of transistor structures included as a portion of the semiconductor integrated circuit;
forming a piezoelectric layer acoustically coupled to the deposited acoustic energy storage layer;
forming a first conductive region electrically coupled to the deposited piezoelectric layer and electrically coupled to the semiconductor integrated circuit;
wherein the acoustic energy storage layer, the piezoelectric layer, and the first conductive region are included as a portion of a first lateral-mode resonator;
wherein forming the acoustic energy storage layer comprises recrystallizing a deposited semiconductor material using a laser.

18. The method of claim 17 , comprising forming an array of lateral-mode resonators upon the surface of the semiconductor integrated circuit, the array including the first lateral mode resonator; and
wherein the semiconductor integrated circuit includes complementary metal-oxide-semiconductor (CMOS) transistor structures.

19. The method of claim 17 , comprising:
forming a dielectric region located upon a surface of the semiconductor integrated circuit, the dielectric region coupled to the deposited acoustic energy storage layer and defining a cavity between the deposited acoustic energy storage layer and the semiconductor integrated circuit;
wherein the acoustic energy storage layer includes a released configuration suspended from the dielectric region.

20. The method of claim 17 , comprising:
forming an acoustic mirror located between the deposited acoustic energy storage layer and the semiconductor integrated circuit.

21. The method of clai

Assignees

• Univ Columbia

Inventors

• Edrees Hassan
• Kymissis Ioannis
• Kinget Peter

Classifications

• H03H9/205

  having multiple resonators (crystal tuning forks H03H9/21) · CPC title

• H03H2009/02188

  Electrically tuning · CPC title

• H03H9/467 Primary

  Post-fabrication trimming of parameters, e.g. center frequency · CPC title

• H01L27/20

  Electricity · mapped topic

• H03H9/2426

  in combination with other electronic elements · CPC title