Transformer composed of a front stage circuit and a rear stage circuit

Patent metadata

Field	Value
Publication number	US-10122288-B2
Application number	US-201515509296-A
Country	US
Kind code	B2
Filing date	Oct 9, 2015
Priority date	Nov 5, 2014
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A transformer includes a front stage circuit and a rear stage circuit. As a front stage circuit, a switch series unit, which is connected in parallel to a power supply, includes odd-numbered switches and even-numbered switches alternately turned ON. Mutual connection points of the respective switches and points at both ends of the switch series unit are regarded as m nodes in total. Capacitors are provided on at least one of a first electrical path combining odd nodes to lead them to a first output port, and a second electrical path combining even nodes to lead them to a second output port. The capacitors are present so as to correspond to at least (m−1) nodes. The rear stage circuit includes an element series unit, which is composed of a pair of semiconductor elements connected in series to each other for conducting operations of mutually opposite polarities, and necessary inductors.

First claim

The invention claimed is:

1. A transformer provided between a power supply and a load, and composed of a front stage circuit and a rear stage circuit, the transformer comprising:
the front stage circuit comprising:
a switch series unit composed of a plurality of switches, the plurality being a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one end of the switch series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit being connected in parallel to the power supply, and
under a condition that mutual connection points of the respective switches and points at both ends of the switch series unit are regarded as nodes, a number of nodes being (m) in total, and the nodes are seen in order of 1 to m th from one end of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and connect the odd nodes to a first output port, the second electrical path being configured to combine even nodes and connect the even nodes to a second output port, the capacitors corresponding to at least (m−1) nodes;

the rear stage circuit comprising:
an element series unit composed of a pair of semiconductor elements that are connected in series to each other and perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being connected to the first output port while the other end thereof being connected to the second output port, and
inductors provided on at least one electrical path of a third electrical path and a fourth electrical path, the third electrical path being configured to combine two additional nodes that are points at the both ends of the element series unit and to connect the two additional nodes to one end of the load, the fourth electrical path being configured to connect a third additional node that is a mutual connection point of the pair of semiconductor elements to another end of the load, the inductors being present so as to correspond to at least two of the three additional nodes; and

a control section configured to control ON/OFF operations of the switches.

2. The transformer according to claim 1 , wherein
under a condition that a time period from a dead-time start time to a dead-time end time is a dead time τ, the dead-time start time being a time at which control for the odd-numbered switches and control for the even-numbered switches are both turned OFF, the dead-time end time being a time at which control for either the odd-numbered switches or the even-numbered switches is turned ON,
the control section, after the dead-time start time, calculates a first half time (τ 1 ) and a second half time(τ 2 ), the first half time (τ 1 ) being calculated on the basis of electric charges that move from the inductors to floating capacitances of the switches while one of thesemiconductor elements is in a conductive state, the second half time (τ 2 ) being calculated on the basis of electric charges that move from the inductors to the floating capacitances of the switches while the other semiconductor element is in a conductive state, and the control section determines the dead time (τ) on the basis of the first half time (τ 1 ) and the second half time (τ 2 ).

3. The transformer according to claim 2 , wherein the control section terminates the dead time (τ) before the electric charges that have moved to the floating capacitances return to the inductors.

4. The transformer according to claim 3 , wherein
assuming that a switching cycle of the switches is (T), an inductance of the inductors is (L), and a resistance value of the load is R 3 , the dead time (τ) satisfies the following relationship:
τ 1 +τ 2 ≤τ≤τ 0 +(τ 2 /2) +τ 1

where

τ
0

=

T
4

-

L

2
⁢

⁢

R
3

τ
1

=

T
2

+

L

⁢

R
3

-

1
2

⁢

(

T
+

2
⁢
L

R
3

)

2

-

32
⁢

⁢
L
⁢

∑

n
=
1

n

⁢

⁢

C
nDS

τ
2

=

T
2

-

L

⁢

R
3

-

1
2

⁢

(

T

Assignees

• Sumitomo Electric Industries
• National Univ Corporation Toyohashi Univ Of Technology

Inventors

• Nakahata Hideaki
• Hirotsu Kenichi
• Ohira Takashi
• Yamada Kyohei
• Egashira Daiya

Classifications

• H02M5/293

  using semiconductor devices only · CPC title

• H02M3/155

  using semiconductor devices only · CPC title

• H02M5/12 Primary

  for conversion of voltage or current amplitude only · CPC title

• H02M5/22 Primary

  using discharge tubes with control electrode or semiconductor devices with control electrode · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title