Apparatus and method for reducing harmonics

Patent metadata

Field	Value
Publication number	US-10122165-B2
Application number	US-201414916219-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	Oct 14, 2013
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

The present invention provides systems and methods for reducing harmonics, for example when using an AC to AC converter to drive a load such as a motor drive. In a first embodiment, a plurality of load driving circuits is provided, each drawing current from a 3-phase AC supply and driving an AC load, wherein each of said load driving circuit includes a 3-phase rectifier, with the rectifiers of the load driving circuits being controlled such that the rectification of the AC supply by the load driving circuits is staggered. In a second embodiment, a load driving circuit comprises an electronic inductor configured to control the DC link voltage and/or current such that the current drawn from the AC supply by the load driving circuit has a stepped profile. The first and second embodiments may be combined.

First claim

What is claimed is:

1. A load driving circuit comprising:
a 3-phase rectifier having an input coupled to a 3-phase AC supply;
a DC link stage;
an inverter having an input coupled to an output of the DC link stage and an output coupled to a load, wherein the inverter converts an output voltage of the DC link stage into a signal for driving the load; and
an electronic inductor configured to control the output voltage and/or output current of the DC link stage such that the current drawn from the AC supply by the load driving circuit has a stepped profile;
wherein said stepped profile is mathematically equivalent to the sum of a first, second and third pulses having first, second and third phase offsets respectively;
wherein said stepped profile is given by:

4
⁢

I

dc
⁢

⁢
1

⁢

cos
⁡

(

n
⁢

⁢
30

)

n
⁢

⁢
π

+

4
⁢

I

dc
⁢

⁢
2

⁢

cos
⁡

(

n
⁢

⁢
α1

)

n
⁢

⁢
π

-

4
⁢

I

dc
⁢

⁢
2

⁢

cos
⁡

(

n
⁢

⁢
α2

)

n
⁢

⁢
π

,

 wherein I dc1 , I dc2 and −I dc2 are the amplitudes of the first, second and third pulses.

2. The load driving circuit as claimed in claim 1 , wherein 30, α1 and α2are the said first, second and third offsets respectively.

3. The load driving circuit as claimed in claim 1 , wherein the stepped profile is shaped such that, in a three-phase system, the sum of the stepped profile for each of the three phases is symmetrical.

4. The load driving circuit as claimed in claim 1 , wherein the stepped profile has a first portion and a second portion, the first and second portions being symmetrical, the first portion comprising a first projection and a second projection, wherein each projection has a duration θ, the first projection starting at a time β after the start of the pulse, the time between the first and second projections being 2β, and the time from the end of the second projection to the end of the portion of the pulse being given by β.

5. The load driving circuit as claimed in claim 4 , wherein the first and second portions of the pulse each have a duration of 120 degrees such that 2β+θ=60.

6. The load driving circuit as claimed in claim 1 , wherein the electronic inductor is configured such that at least one harmonic of the current drawn from the AC supply is eliminated.

7. A system comprising a plurality of load driving circuits, each of the load driving circuits drawing current from a 3-phase AC supply and driving an AC load, wherein each of said load driving circuit comprises:
a 3-phase rectifier having an input coupled to the AC supply;
a DC link stage having an input coupled to the output of the rectifier; and
an inverter having an input coupled to an output of the DC link stage and an output coupled to the respective load, wherein the inverter converts a DC link voltage into a signal for driving the respective AC load,
wherein:
each DC link stage includes an electronic inductor configured to control the output voltage and/or output current of the DC link stage; and
the rectifiers of the load driving circuits are arranged such that the rectification of at least some of the load driving circuits is staggered.

8. The system as claimed in claim 7 , wherein each of the plurality of inverters drives a different load.

9. The system as claimed in claim 7 , wherein each electronic inductor is controlled such that substantially square wave current pulses are drawn from the AC supply by the respective load driving circuit.

10. The system as claimed in claim 7 , wherein the rectifiers of at least some of the plurality of load driving circuits are thyristor-based rectifiers in which the thyristors are controlled in order to provide said staggered rectification.

11. The system as claimed in claim 7 , further comprising a control module for controlling the electronic inductors.

12. The system as claimed in claim 7 , wherein at least some of the electronic inductors are in communication with other electronic inductors.

13. The system as claimed in claim 7 , wherein each of said load driving circuits is a load driving circuit.

14. A method comprising controlling an electronic inductor provided between a 3-phase rectifier and a DC link stage of a load driving circuit such that the output voltage and/or output current of the DC link stage is controlled such that the current drawn from a 3-pha

Assignees

• Danfoss Power Electronics As

Inventors

• Zare Firuz

Classifications

• H02M1/4225 Primary

  using a non-isolated boost converter · CPC title

• Y02E40/40

  Arrangements for reducing harmonics · CPC title

• H02M5/458

  using semiconductor devices only · CPC title

• H02J3/01

  Arrangements for reducing harmonics or ripples · CPC title

• H02M1/4216

  operating from a three-phase input voltage (H02M1/4233 takes precedence) · CPC title