FinFet with heterojunction and improved channel control

Patent metadata

Field	Value
Publication number	US-10121896-B2
Application number	US-201514925777-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Jun 26, 2013
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first crystalline semiconductor material of the fin and the second crystalline semiconductor material of the fin support form a first heterojunction in between. A gate, gate dielectric, and/or isolation dielectric can be positioned to improve control within the channel.

First claim

The invention claimed is:

1. A method of making a first transistor and a second transistor, the method comprising:
epitaxially forming a first region and a second region above a common buffer layer, the first region formed of a first crystalline semiconductor material, the second region formed of a second crystalline semiconductor material different from the first semiconductor material, and the common buffer layer formed of a third crystalline semiconductor material;
forming a first fin from the first region, the first fin including a first channel region of the first transistor between a source region of the first transistor and a drain region of the first transistor, the first fin on a first fin support;
forming the first fin support from the common buffer layer, the first crystalline semiconductor material of the first fin and the third crystalline semiconductor material of the first fin support forming a first heterojunction in between;
forming a second fin from the second region, the second fin including a second channel region of the second transistor between a source region of the second transistor and a drain region of the second transistor, the second fin on a second fin support; and
forming the second fin support from the common buffer layer, the second crystalline semiconductor material of the second fin and the third crystalline semiconductor material of the second fin support forming a second heterojunction in between.

2. The method of claim 1 wherein the third crystalline semiconductor material is SiGeSn.

3. The method of claim 2 wherein the third crystalline semiconductor material is lattice-matched to an underlying semiconductor layer.

4. The method of claim 3 wherein the underlying semiconductor layer is germanium.

5. The method of claim 1 wherein the first crystalline semiconductor material has a first bandgap, the second semiconductor material has a second bandgap, and the third semiconductor material has a third bandgap, the third bandgap wider than the first bandgap and the second bandgap.

6. The method of claim 1 wherein the third crystalline semiconductor material of the first fin support induces a first stress in the first channel region of the first transistor and the third crystalline semiconductor material of the second fin support induces a second stress in the second channel region of the second transistor, the first stress different from the second stress.

7. The method of claim 6 wherein the first stress is tensile and the second stress is compressive.

8. The method of claim 1 wherein the first transistor is an n-type transistor and the second transistor is a p-type transistor.

9. The method of claim 1 further comprising:
forming a first isolation oxide running along opposite sides of the first fin support and electrically isolating the first fin support from adjacent fin supports, the first isolation oxide positioned only below the first heterojunction;
forming a first gate dielectric including: (i) a first part overlying sides and top of the first fin, the first part conformally covering the first fin and having a first thickness and (ii) a second part conformally covering the first fin support between the first heterojunction and the isolation oxide and having about the first thickness; and
forming a first gate conformally covering the first part and the second part of the first gate dielectric.

10. A structure comprising:
a plurality of first parallel fins formed of a first crystalline semiconductor material, the first fins on first fin supports formed of a second crystalline semiconductor material, wherein the first crystalline semiconductor material and the second crystalline semiconductor material meet at a heterojunction; and
a plurality of second parallel fins formed of a third crystalline semiconductor material different from the first crystalline semiconductor material, the second fins on second fin supports formed of the second crystalline semiconductor material, wherein the third crystalline semiconductor material and the second crystalline semiconductor material meet at a heterojunction,
wherein the first fin supports and the second fin support are continuous with a common buffer layer of the second crystalline semiconductor material,
wherein the first crystalline semiconductor material has a first bandgap, the second semiconductor material has a second bandgap, and the third crystalline semiconductor material has a third bandgap, the second bandgap wider than the first bandgap and wider than the third bandgap.

11. The structure of claim 10 wherein the second crystalline semiconductor material is SiGeSn.

12. The structure of claim 11 wherein the second crystalline semiconductor material is lattice-matched to an underlying semiconductor layer.

13. The structure of claim 12 wherein the underlying semiconductor layer is germanium.

14. The structure of claim 10 wherein the first crystalline semiconductor material has a first bandgap, the second semiconductor material has a second bandgap, and the third semiconductor material has a third bandgap, the second bandgap wider than the first bandgap and the third bandgap.

15. The structure of claim 10 wherein the second crystalline semiconductor material of the first fin supports induces a first stress in the first fins and the second crystalline semiconductor material of the second fin supports induces a second stress in the second fins, the first stress different from the second stress.

16. The structure of claim 15 wherein the first stress is tensile and the second stress is compressive.

Assignees

• Synopsys Inc

Inventors

• Moroz Victor
• Smith Stephen L
• Lu Qiang

Classifications

• H01L29/66795

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic