Nanowire transistor fabrication with hardmask layers

Patent metadata

Field	Value
Publication number	US-10121861-B2
Application number	US-201313996850-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

First claim

What is claimed is:

1. A nanowire transistor, comprising:
a plurality of nanowire channels formed above a microelectronic substrate, wherein the plurality of the nanowire channels are spaced apart from one another; wherein one nanowire channel of the plurality of nanowire channels is positioned farther from the microelectronic substrate than the remainder of the plurality of nanowire channels;
a source abutting a first end of each nanowire channel of the plurality of nanowire channels;
a drain abutting a second end of each nanowire channel of the plurality of nanowire channels;
a first spacer positioned proximate the first end of each nanowire channel of the plurality of nanowire channels and a second spacer positioned proximate the second end of each nanowire channel of the plurality of nanowire channels, wherein the first spacer physically contacts each nanowire channel of the plurality of nanowire channels and wherein the second spacer physically contacts each nanowire channel of the plurality of nanowire channels;
a hardmask layer comprising a first hardmask portion and a second hardmask portion, wherein an entirety of the hardmask layer is formed above the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, wherein a hardmask material of the hardmask layer and a spacer material of the first spacer and the second spacer are different and selectively removable with respect to each other; and
a gate dielectric material abutting a top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, wherein the gate dielectric material is positioned between the first hardmask portion and the second hardmask portion;
wherein the first hardmask portion abuts the first spacer, abuts the source, abuts the gate dielectric material, and abuts the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, such that the first hardmask portion covers a portion of the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels between the source and the gate dielectric material, such that the first hardmask portion extends between the gate dielectric material and the first end of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, and separates the first spacer from the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, and wherein the second hardmask portion abuts the second spacer, abuts the drain, abuts the gate dielectric material, and abuts the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, such that the second hardmask portion covers another portion of the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels between the drain and the gate dielectric material, such that the second hardmask portion extends between the gate dielectric material and the second end of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, and separates the second spacer from the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels.

2. The nanowire transistor of claim 1 , further including a gate electrode material abutting the gate dielectric material.

3. The nanowire transistor of claim 1 , wherein the first hardmask portion and the second hardmask portion comprise a material selected from the group consisting of silicon, porous silicon, amorphous silicon, silicon nitride, silicon oxynitride, silicon oxide, silicon dioxide, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum silicate, lanthanum oxide, and polymer materials.

4. The nanowire transistor of claim 1 , wherein the plurality of nanowire channels comprise silicon germanium.

5. The nanowire transistor of claim 1 , wherein the plurality of nanowire channels comprise silicon.

6. The nanowire transistor of claim 1 , wherein the source and the drain comprise n-doped silicon.

7. The nanowire transistor of claim 1 , wherein the source and the drain comprise p-doped silicon.

8. The nanowire transistor of claim 1 , wherein the source and the drain comprise p-doped silicon germanium.

9. The nanowire transistor of claim 1 , wherein the gate dielectric material comprises a material selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium oxide, and lead zinc niobate.

10. The nanowire transistor of claim 2 , wherein the gate electrode material comprises a material selected from the group consisting of titanium, tungsten, tantalum, aluminum, copper, ruthenium, cobalt, chromium, iron, palladium, platinum, molybdenum, manganese, vanadium, gold, silver, niobium, and alloys thereof.

11. The nanowire transistor of claim 2 , wherein the gate electrode material comprises a metal carbide.

12. The nanowire transistor of claim 11 , wherein the metal carbide comprises a material selected from the group consisting of titanium carbide, zirconium carbide, tantalum carbide, and tungsten carbide.

13. The nanowire transistor of claim 2 , wherein the gate electrode material comprises a metal oxide.

Assignees

• Intel Corp

Inventors

• Sung Seung Hoon
• Kim Seiyon
• Kuhn Kelin
• Rachmady Willy
• Kavalieros Jack

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• B41N2210/14

  characterised by macromolecular organic compounds · CPC title

• B41F17/08

  for printing on filamentary or elongated articles, or on articles with cylindrical surfaces · CPC title

• B41N10/04

  multi-layer · CPC title

• B41N2210/04

  Intermediate layers · CPC title