Nano-tube MOSFET technology and devices

Patent metadata

Field	Value
Publication number	US-10121857-B2
Application number	US-201514702592-A
Country	US
Kind code	B2
Filing date	May 1, 2015
Priority date	Dec 31, 2008
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

First claim

We claim:

1. A method for manufacturing a metal oxide semiconductor field effect
transistor (MOSFET) comprising:
opening a plurality of deep trenches between lightly doped pillars and substantially filling the deep trench with alternating N and P doped multiple epitaxial layers overflowing and covering a top surface of the semiconductor substrate with a top epitaxial layer wherein the epitaxial layers form charge balanced nano tubes for functioning as conducting channels extending along a sidewall direction; and
forming a body region encompassing source region surrounding a gate of the MOSFET disposed near a top surface of the pillar comprising the volume of the semiconductor substrate for conducting a current through the nano tubes to a drain region disposed on the bottom of the semiconductor substrate.

2. The method of claim 1 further comprising a step of:
filling a remaining central gap with a gap filler.

3. The method of claim 2 wherein:
said step of filling said central gap with said gap filler further comprising a step of forming said gap filler as a lightly doped silicon with a dopant concentration equal to or less than 10% of a dopant concentration of adjacent nano tubes.

4. The method of claim 2 wherein:
said step of filling said central gap with said gap filler further comprising a step of forming an oxide layer to fill said central gap.

5. The method of claim 2 wherein:
said step of filling said central gap with said gap filler further comprising a step of depositing a dielectric layer in said central gap.

6. The method of claim 2 further comprising:
removing the epitaxial layer from a top surface down to original Pillar surface by a CMP (Chemical Mechanical Polishing) process and growing an N-epitaxial layer with a thickness substantially between 1 to 5 microns.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Yilmaz Hamza
• Ng Daniel
• Guan Lingping
• Bhalla Anup
• Ma Wilson
• Ho Moses
• Chen John

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H01L29/66712

  Electricity · mapped topic

• H01L29/0676 Primary

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic

• H01L29/7802

  Electricity · mapped topic