Devices related to barrier for metallization of gallium based semiconductor

Patent metadata

Field	Value
Publication number	US-10121780-B2
Application number	US-201615238236-A
Country	US
Kind code	B2
Filing date	Aug 16, 2016
Priority date	Nov 16, 2011
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element.

First claim

What is claimed is:

1. A heterojunction bipolar transistor structure comprising:
a collector layer including gallium arsenide; and
a capacitor structure over the collector layer, the capacitor structure including (i) an emitter that includes indium gallium phosphide and a ledge, (ii) a metal layer over the emitter, and (iii) a tantalum nitride layer over the collector layer and the emitter such that at least a portion of the collector layer and at least a portion of the emitter are within a footprint of the tantalum nitride layer, the tantalum nitride layer being configured to separate and function as a barrier between the metal layer and the emitter, and the collector layer and the emitter being included in a heterojunction bipolar transistor.

2. The heterojunction bipolar transistor structure of claim 1 wherein the footprint of the tantalum nitride layer is smaller than a footprint of the metal layer.

3. The heterojunction bipolar transistor structure of claim 1 further comprising a base layer disposed between the collector layer and the emitter.

4. The heterojunction bipolar transistor structure of claim 3 wherein the base layer includes p-type gallium arsenide and the gallium arsenide of the collector layer includes n-type gallium arsenide.

5. The heterojunction bipolar transistor structure of claim 3 further comprising a second metal layer disposed over and in electrical communication with the base layer, the tantalum nitride layer being nested within a region defined by a footprint of the second metal layer.

6. The heterojunction bipolar transistor structure of claim 1 wherein the tantalum nitride layer has a first side in physical contact with the emitter.

7. The heterojunction bipolar transistor structure of claim 6 wherein the tantalum nitride layer has a second side in physical contact with the metal layer.

8. The heterojunction bipolar transistor structure of claim 1 wherein the emitter includes an implant configured to disrupt a crystal lattice of the emitter.

9. The heterojunction bipolar transistor structure of claim 1 wherein a capacitance density of the capacitor structure is at least 2.0 femtofarads per square micrometer.

10. A capacitor structure comprising:
an indium gallium phosphide layer including a ledge;
a metal layer over the indium gallium phosphide layer, a tantalum nitride layer configured to separate and function as a barrier layer between the metal layer and the indium gallium phosphide layer;
a gallium arsenide layer, the indium gallium phosphide layer being disposed between the gallium arsenide layer and the tantalum nitride layer; the gallium arsenide layer, the indium gallium phosphide layer, the metal layer, and the tantalum nitride layer being included in a metal-insulator-semiconductor capacitor;
a contact to the gallium arsenide layer, a passivation structure being disposed laterally between the contact and the indium gallium phosphide layer; and
a second metal layer connected to the contact, the second metal layer being spaced apart from the metal layer, and the tantalum nitride layer being nested within a region defined by a footprint of the second metal layer.

11. The capacitor structure of claim 10 wherein the tantalum nitride layer has a smaller footprint than the metal layer.

12. The capacitor structure of claim 10 wherein the tantalum nitride layer is in physical contact with the indium gallium phosphide layer.

13. The capacitor structure of claim 10 wherein a capacitance density of the capacitor is at least 2.0 femtofarads per square micrometer.

14. The capacitor structure of claim 10 wherein the indium gallium phosphide layer includes an implant that impacts an operating voltage range of the capacitor.

15. The capacitor structure of claim 10 wherein the indium gallium phosphide layer includes a surface in physical contact with the tantalum nitride layer and a passivation structure.

16. A semiconductor die comprising:
a gallium arsenide layer included in a collector of a heterojunction bipolar transistor;
a semiconductor layer that includes a wide bandgap semiconductor lattice-matched to gallium arsenide, the semiconductor layer being included in an emitter of the heterojunction bipolar transistor;
a tantalum nitride layer over the collector and the emitter such that at least a portion of the collector and at least a portion of the emitter are within a footprint of the tantalum nitride layer; and
a metal layer over the semiconductor layer, the tantalum nitride layer configured to separate and function as a barrier layer between the metal layer and the semiconductor layer.

17. The semiconductor die of claim 16 further comprising a second metal layer spaced apart from the metal layer.

18. The semiconductor die of claim 17 wherein the tantalum nitride layer is nested within a region defined by a footprint of the second metal layer.

19. The semiconductor die of claim 16 wherein the wide bandgap semiconductor lattice-matched to gallium arsenide includes indium gallium phosphide.

20. The semiconductor die of claim 16 wherein the semiconductor layer includes a ledge.

21. The semiconductor die of claim 16 further comprising another gallium arsenide layer disposed below the semiconductor layer and included in a base of the heterojunction bipolar transistor.

Assignees

• Skyworks Solutions Inc

Inventors

• Cismaru Cristian
• Zampardi Jr Peter J

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title