Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
US10121775B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10121775-B2 |
| Application number | US-201415038034-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 7, 2014 |
| Priority date | Nov 21, 2013 |
| Publication date | Nov 6, 2018 |
| Grant date | Nov 6, 2018 |
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Described is an optoelectronic semiconductor chip ( 1 ) with a built-in bridging element ( 9, 9 A) for overvoltage protection.
Opening claim text (preview).
The invention claimed is: 1. An optoelectronic semiconductor chip comprising: a semiconductor layer sequence containing semiconductor material, which sequence comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type and an active zone with a pn junction, which is formed between the first and the second semiconductor region; a carrier, on which the semiconductor layer sequence is arranged; a first contact, which is provided for electrical connection of the first semiconductor region; a second contact different from the first contact, which second contact is provided for electrical connection of the second semiconductor region; and a bridging element connected parallel or antiparallel to the semiconductor layer sequence, which bridging element comprises a nonlinear electrical resistance, which is higher in the case of an operating voltage of the optoelectronic semiconductor chip in the forward direction than an electrical resistance of the semiconductor layer sequence and is lower in the case of overvoltages in the reverse direction than the electrical resistance of the semiconductor layer sequence, such that electrical charge is discharged via the bridging element in the case of overvoltages, wherein the bridging element comprises at least one bridging layer, which is arranged outside the semiconductor material of the semiconductor layer sequence, wherein the semiconductor layer sequence comprises a recess, wherein the second contact comprises a contact element, which is arranged in the recess, wherein the contact element is surrounded peripherally by the bridging element, wherein the bridging element connects together the first and second semiconductor regions and/or one semiconductor region with the respective contact, and wherein the first contact comprises a contact layer, which is interrupted by an opening, through which the contact element extends. 2. The optoelectronic semiconductor chip according to claim 1 , wherein the bridging layer is not an epitaxial layer. 3. The optoelectronic semiconductor chip according to claim 1 , wherein the bridging element and/or the bridging layer contain(s) a polycrystalline electroceramic material. 4. The optoelectronic semiconductor chip according to claim 1 , wherein the bridging element connects together the first and second contacts. 5. The optoelectronic semiconductor chip according to claim 1 , wherein the bridging element is provided at the semiconductor layer sequence. 6. The optoelectronic semiconductor chip according to claim 1 , wherein the semiconductor layer sequence comprises a first major face facing the carrier and a second major face remote from the carrier and one side face, which extends at an angle to the first and second major faces, and wherein the bridging layer is arranged on the side face. 7. The optoelectronic semiconductor chip according to claim 1 , wherein the recess delimited by an inner face of the semiconductor layer sequence, and wherein the bridging layer is arranged on the inner face. 8. The optoelectronic semiconductor chip according to claim 1 , wherein the first contact comprises a first contact layer and the second contact comprises a second contact layer, the first contact layer and the second contact layer being connected together by the bridging element. 9. The optoelectronic semiconductor chip according to claim 1 , wherein the bridging element comprises at least one of the following materials: zinc oxide, strontium oxide, strontium titanate, titanium oxide, silicon carbide. 10. The optoelectronic semiconductor chip according to claim 1 , wherein the bridging element contains at least one of the following material additives: bismuth oxide, antimony oxide, cobalt oxide, manganese oxide, nickel oxide, chromium oxide and silicon oxide. 11. The optoelectronic semiconductor chip according to claim 1 , wherein the bridging element is a varistor, a Schottky diode or a Zener diode. 12. An optoelectronic semiconductor chip comprising: a semiconductor layer sequence containing semiconductor material, which sequence comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type and an active zone with a pn junction, which is formed between the first and the second semiconductor region; a carrier, on which the semiconductor layer sequence is arranged; a first contact, which is provided for electrical connection of the first semiconductor region, a second contact different from the first contact, which second contact is provided for electrical connection of the second semiconductor region; and a bridging element connected parallel or antiparallel to the semiconductor layer sequence, which bridging element comprises a nonlinear electrical resistance, which is higher in the case of an operating voltage of the optoelectronic semiconductor chip in the forward direction than an electrical resistance of the semiconductor layer sequence and is lower in the case of overvoltages in the reverse direction than the electrical resistance of the semiconductor layer sequence, such that electrical charge is discharged via the bridging element in the case of overvoltages, wherein the bridging element comprises at least one bridging layer, which is arranged outside the semiconductor material of the semiconductor layer sequence, wherein the bridging element is provided at the carrier, and wherein the carrier comprises a base body and at least one connection element, which is connected electrically with the first or second contact and is at least partially embedded into the base body and/or is arranged on the base body, and wherein the carrier comprises a first connection element, which is connected electrically with the first contact, and a second connection element, which is connected electrically with the second contact, and wherein the first and second connection elements are connected together by the bridging element.
Package configurations · CPC title
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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