Multi-die inductors with coupled through-substrate via cores

Patent metadata

Field	Value
Publication number	US-10121739-B1
Application number	US-201715584881-A
Country	US
Kind code	B1
Filing date	May 2, 2017
Priority date	May 2, 2017
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed around the first TSV. The second die includes a second TSV coupled to the first TSV and a second substantially helical conductor disposed around the second TSV. The first substantially helical conductor is configured to induce a change in a magnetic field in the first and second TSVs in response to a first changing current in the first substantially helical conductor, and the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.

First claim

I claim:

1. A semiconductor device, comprising:
a first die including:
a first through-substrate via (TSV) extending at least substantially through the first die, and
a first substantially helical conductor disposed around the first TSV; and
a second die including:
a second TSV coupled to the first TSV, and
a second substantially helical conductor disposed around the second TSV,
wherein the second TSV is coupled to the first TSV by a solder connection, and wherein the solder connection is separated from the first and second TSVs by a barrier material configured to prevent solder diffusion into the first and second TSVs.

2. The semiconductor device of claim 1 , wherein the first substantially helical conductor is configured to induce a change in a magnetic field in the first and second TSVs in response to a first changing current in the first substantially helical conductor, and wherein the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.

3. The semiconductor device of claim 1 , wherein the solder connection comprises a magnetic material.

4. The semiconductor device of claim 1 , wherein the first TSV and the second TSV are coaxially aligned.

5. The semiconductor device of claim 1 , wherein the first and second TSVs comprise a ferromagnetic or a ferrimagnetic material.

6. The semiconductor device of claim 1 , wherein the first TSV is separated from the first substantially helical conductor by an insulating material, and the second TSV is separated from the second substantially helical conductor by an insulating material.

7. The semiconductor device of claim 1 , wherein the first substantially helical conductor comprises more than one turn around the first TSV, and the second substantially helical conductor comprises more than one turn around the second TSV.

8. The semiconductor device of claim 1 , wherein the first substantially helical conductor is coaxially aligned with the first TSV.

9. The semiconductor device of claim 1 , wherein the second substantially helical conductor is coaxially aligned with the second TSV.

10. A semiconductor device, comprising:
a first die including:
a first through-substrate via (TSV) extending at least substantially through the first die,
a second TSV extending at least substantially through the first die, and
a first substantially helical conductor disposed around one of the first and second TSVs,
a second die including:
a third TSV coupled to the first TSV,
a fourth TSV coupled to the second TSV, and
a second substantially helical conductor disposed around one of the third and fourth TSVs,
wherein the third TSV is coupled to the first TSV by a first solder connection, wherein the fourth TSV is coupled to the second TSV by a second solder connection, and wherein the first solder connection is separated from the first and third TSVs by a barrier material configured to prevent solder diffusion into the first and third TSVs.

11. The semiconductor device of claim 10 , wherein the first substantially helical conductor is configured to induce a change in a magnetic field in the first, second, third and fourth TSVs in response to a first changing current in the first substantially helical conductor, and wherein the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the TSV around which the second substantially helical conductor is disposed.

12. The semiconductor device of claim 10 , wherein the first, second, third and fourth TSVs comprise a ferromagnetic or a ferrimagnetic material.

13. The semiconductor device of claim 10 , wherein the second TSV is coupled to the first TSV by an upper coupling member above the first substantially helical conductor.

14. The semiconductor device of claim 13 , wherein the upper coupling member comprises a ferromagnetic or a ferrimagnetic material.

15. The semiconductor device of claim 10 , wherein the fourth TSV is coupled to the third TSV by a lower coupling member below the second substantially helical conductor.

16. The semiconductor device of claim 15 , wherein the lower coupling member comprises a ferromagnetic or a ferrimagnetic material.

17. The semiconductor device of claim 10 , wherein the third and fourth TSVs extend at least substantially through the second die.

18. The semiconductor device of claim 10 , wherein the second solder connection is separated from the second and fourth TSVs by a barrier material configured to prevent solder diffusion into the second and fourth TSVs.

19. The semiconductor device of claim 10 , wherein the first and second solder connections comprise a magnetic material.

20. The semiconductor device of claim 10 , wherein the first substantially helical conductor is disposed around the first TSV, and the second substantially helical conductor is disposed around the third TSV.

Assignees

• Micron Technology Inc

Inventors

• Kirby Kyle K

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title