Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
US10121732B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10121732-B2 |
| Application number | US-201715784472-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 16, 2017 |
| Priority date | Feb 3, 2017 |
| Publication date | Nov 6, 2018 |
| Grant date | Nov 6, 2018 |
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A semiconductor device includes: a base plate including a metallic base plate and an insulating film provided on the metallic base plate; a semiconductor chip provided on the base plate; a control board disposed above the semiconductor chip; and a relay terminal connected to a signal electrode of the semiconductor chip through a signal line wire, extending to the control board, and connected to the control board, wherein the relay terminal is directly fixed to the insulating film of the base plate.
Opening claim text (preview).
The invention claimed is: 1. A semiconductor device comprising: a base plate including a metallic base plate and an insulating film provided on the metallic base plate; a semiconductor chip provided on the base plate; a control board disposed above the semiconductor chip; and a relay terminal connected to a signal electrode of the semiconductor chip through a signal line wire, extending to the control board, and connected to the control board, wherein the relay terminal is directly fixed to the insulating film of the base plate. 2. The semiconductor device according to claim 1 , further comprising a main electrode terminal connected to a main electrode of the semiconductor chip through a main line wire and directly fixed to the insulating film of the base plate. 3. The semiconductor device according to claim 1 , comprising: a circuit pattern provided on an upper surface of the base plate; and a main line wire connecting a main electrode of the semiconductor chip to the circuit pattern, wherein the relay terminal is disposed on an inner side of the base plate than the circuit pattern on an upper surface of the base plate. 4. The semiconductor device according to claim 1 , wherein the relay terminal includes a plurality of terminals disposed in a zig-zag manner on an upper surface of the base plate. 5. The semiconductor device according to any claim 1 , wherein the semiconductor chip is made of a wide-band-gap semiconductor. 6. An electric power conversion device comprising: a main conversion circuit including the semiconductor device according to claim 1 , converting input power and outputting the converted power, and a control circuit outputting a control signal for controlling the main conversion circuit to the main conversion circuit.
between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title
between laterally-adjacent chips · CPC title
Package configurations · CPC title
being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title
not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title
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