Laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor

US10121591B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10121591-B2
Application numberUS-201715643826-A
CountryUS
Kind codeB2
Filing dateJul 7, 2017
Priority dateAug 7, 2012
Publication dateNov 6, 2018
Grant dateNov 6, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A laminated ceramic capacitor that includes a ceramic laminated body having a stacked plurality of ceramic dielectric layers and a plurality of internal electrodes opposed to each other with the ceramic dielectric layers interposed therebetween, and external electrodes on the outer surface of the ceramic laminated body and electrically connected to the internal electrodes. The internal electrodes contain Ni and Sn, a proportion of the Sn/(Ni+Sn) ratio is 0.001 or more in molar ratio is 75% or more in a region of the internal electrode at a depth of 20 nm from a surface opposed to the ceramic dielectric layer, and the proportion of the Sn/(Ni+Sn) ratio is 0.001 or more in molar ratio is less than 40% in a central region in a thickness direction of the internal electrode.

First claim

Opening claim text (preview).

The invention claimed is: 1. A laminated ceramic capacitor comprising: a ceramic laminated body having a plurality of stacked ceramic dielectric layers and a plurality of internal electrodes opposed to each other with the ceramic dielectric layers interposed therebetween; and an external electrode on an outer surface of the ceramic laminated body and electrically connected to the internal electrodes, wherein the internal electrodes contain Ni and Sn, in a region of the internal electrode at a depth of 20 nm from a surface of the internal electrode opposed to the ceramic dielectric layer a proportion of a ratio of Sn to a total amount of Sn and Ni is 0.001 or more in molar ratio is 75% or more; and in a central region in a thickness direction of the internal electrode a proportion of the ratio of Sn to the total amount of Sn and Ni is 0.001 or more in molar ratio is less than 40%.

Assignees

Inventors

Classifications

  • H01G4/008Primary

    Selection of materials · CPC title

  • Fried electrodes · CPC title

  • Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00 · CPC title

  • Form of non-self-supporting electrodes · CPC title

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What does patent US10121591B2 cover?
A laminated ceramic capacitor that includes a ceramic laminated body having a stacked plurality of ceramic dielectric layers and a plurality of internal electrodes opposed to each other with the ceramic dielectric layers interposed therebetween, and external electrodes on the outer surface of the ceramic laminated body and electrically connected to the internal electrodes. The internal electrod…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01G4/008. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).