Electronic device

Patent metadata

Field	Value
Publication number	US-10121537-B2
Application number	US-201715704995-A
Country	US
Kind code	B2
Filing date	Sep 14, 2017
Priority date	Dec 2, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.

First claim

What is claimed is:

1. An electronic device including a semiconductor memory, wherein the semiconductor memory comprises:
a plurality of resistive storage cells each structured to exhibit different resistance values for storing data;
a reference resistance cell;
a comparison block electrically coupled to the plurality of resistive storage cells through a first input terminal and the reference resistance cell through a second input terminal, the comparison block operable to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal;
a first clamp part having terminals including a first terminal coupled to the plurality of resistive storage cells, a second terminal coupled to the first input terminal, and a third terminal coupled to a first node, and operable to control a maximum current amount of the cell current depending on a voltage level of the first node;
a second clamp part coupled between the reference resistance cell and the second input terminal, and operable to control a maximum current amount of the reference current depending on the voltage level of the first node;
a voltage stabilization block electrically coupled to the first clamp part through the first node and operable to stabilize a voltage of the first node during a charging or a discharging period; and
a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.

2. The electronic device of claim 1 , wherein the semiconductor memory further comprises:
a clamp voltage generation block coupled to the first node and operable to generate a clamp voltage and apply the generated clamp voltage to the first node.

3. The electronic device of claim 2 , wherein the voltage stabilization block comprises:
a plurality of capacitors coupled in parallel; and
a stabilization clamp voltage generation unit coupled to first ends of the capacitors and operable to generate a stabilization clamp voltage which has the same level as the clamp voltage, and apply the stabilization clamp voltage to the first ends the plurality of capacitors.

4. The electronic device of claim 2 , wherein the voltage stabilization block comprises:
a plurality of capacitors coupled in parallel;
a stabilization clamp voltage generation unit operable to generate a stabilization clamp voltage which has the same level as the clamp voltage; and
a coupling unit coupled between the stabilization clamp voltage generation unit and first ends of the capacitors and operable to drive the capacitors depending on a comparison result of a voltage across the capacitors and the stabilization clamp voltage, in the charging period or the discharging period.

5. The electronic device of claim 1 , wherein the charging period includes a point of time when a read operation is started, and the discharging period includes a point of time when the read operation is ended.

6. The electronic device of claim 1 , wherein the comparison block senses data of a resistive storage cell selected among the plurality of resistive storage cells, by comparing the cell current and the reference current.

7. The electronic device of claim 1 , wherein the semiconductor memory further comprises:
a bit line to which the first terminals of the plurality of resistive storage cells are coupled, wherein the bit line is coupled with the first clamp part; and
a source line to which second terminals of the plurality of resistive storage cells are coupled.

8. The electronic device of claim 7 , wherein the semiconductor memory further comprises:
a plurality of additional resistive storage cells each structured to exhibit different resistance values for storing data;
an additional reference resistance cell;
an additional comparison block electrically coupled to the plurality of additional resistive storage cells through a third input terminal and the additional reference resistance cell through a fourth input terminal, the additional comparison block operable to compare a corresponding cell current flowing through the third input terminal and a corresponding reference current flowing through the fourth input terminal;
an additional first clamp part having terminals including a first terminal coupled to the plurality of additional resistive storage cells, a second terminal coupled to the third input terminal, and a third terminal coupled to the first node, and operable to control a maximum current amount of the corresponding cell current depending on the voltage level of the first node; and
an additional second clamp part coupled between the additional reference resistance cell and the fourth input terminal, and operable to control a maximum current amount of the corresponding reference current depending on the voltage level of the first node.

9. The electronic device of claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;
an operation unit configured to perform an operation based on a result that the control unit decodes the command; and
a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,
wherein the semiconductor memory is part of the memory unit in the microprocessor.

10. The electronic device of claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;
a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and
a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
wherein the semiconductor memory that is part of the cache memory unit in the processor.

11. The electronic device of claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;
an auxiliary memory device configured to store a program for decoding the command and the information;
a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and
an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,
wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

12. The electronic device of claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply;
a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;
a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and
an interface configured to perform communication between at least one of the storage device, the controller a

Assignees

• Sk Hynix Inc

Inventors

• Rho Kwang-Myoung

Classifications

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C2013/0042

  Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB] · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title