Implementing eFuse visual security of stored data using EDRAM

Patent metadata

Field	Value
Publication number	US-10121530-B2
Application number	US-201715587713-A
Country	US
Kind code	B2
Filing date	May 5, 2017
Priority date	Nov 23, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuitry having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

First claim

What is claimed is:

1. A method for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), said method comprising:
providing an EDRAM;
providing an eFuse having an initial state of a logical 0; said EDRAM and said eFuse having a same bit count; and
providing an exclusive OR (XOR) gate receiving respective outputs of said eFuse and said EDRAM, said XOR gate providing an output data combination enabling EDRAM random data to be known at wafer test; and enabling said eFuse to be programmed to provide any logical value out of the output data combination, generating a control signal indicating EDRAM data ready for being read with filtering by said eFuse via said XOR gate.

2. The method as recited in claim 1 includes generating said control signal using a busy signal from said eFuse to indicate that an eFuse read has not completed.

3. The method as recited in claim 1 wherein said eFuse has a busy signal used to indicate that an eFuse read has not completed, and includes using said eFuse busy signal to provide said control signal for reading said XOR gate.

4. The method as recited in claim 1 includes providing a capture latch receiving respective outputs of said XOR gate, said capture latch receiving said control signal for reading said XOR gate.

Assignees

• IBM

Inventors

• Christensen Todd A
• Erickson Karl R
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• G11C11/4078 Primary

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title