Semiconductor memory device for applying different bias voltages and operating method thereof

Patent metadata

Field	Value
Publication number	US-10121529-B2
Application number	US-201715633417-A
Country	US
Kind code	B2
Filing date	Jun 26, 2017
Priority date	Sep 22, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells connected to a plurality of word lines, respectively;
a peripheral circuit configured to apply a program voltage to a selected word line among the plurality of word lines; and
a control logic configured to control the peripheral circuit to apply pre-bias voltages to the plurality of word lines, respectively, before the program voltage is applied to the selected word line,
wherein the pre-bias voltages are determined based on relative positions of the plurality of word lines.

2. The semiconductor memory device according to claim 1 ,
wherein the plurality of word lines are grouped into a plurality of word line groups, and
wherein the closer a word line group among the plurality of word line groups is to a first-programmed memory cell in the memory cell array, the lower a pre-bias voltage to be applied to word lines included in the word line group is.

3. The semiconductor memory device according to claim 1 ,
wherein the plurality of word lines are grouped into a plurality of word line groups,
wherein the memory cells are programmed in a sequence from a memory cell adjacent to a source select transistor, and
wherein the closer a word line group among the plurality of word line groups is to a drain select transistor in the memory cell array, the greater a pre-bias voltage to be applied to word lines included in the word line group is.

4. The semiconductor memory device according to claim 3 , wherein each of the plurality of word line groups includes the same number of word lines.

5. The semiconductor memory device according to claim 3 , wherein the closer the word line group among the plurality of word line groups is to the source select transistor in the memory cell array, the greater the number of word lines included in the word line group is.

6. The semiconductor memory device according to claim 3 , wherein a pre-bias voltage that is applied to word lines included in a word line group to which the selected word line belongs has a default value, and the pre-bias voltage that is applied to the plurality of word lines disposed between the word line group to which the selected word line belongs and the source select transistor also has the default value.

7. The semiconductor memory device according to claim 3 , wherein the control logic determines a precharge voltage to be applied to a common source line based on a position of the selected word line.

8. The semiconductor memory device according to claim 7 , wherein the control logic controls the peripheral circuit such that the closer the selected word line is to the source select transistor, the greater the precharge voltage to be applied to the common source line is.

9. The semiconductor memory device according to claim 1 ,
wherein the plurality of word lines are grouped into a plurality of word line groups,
wherein the memory cells are programmed in a sequence from a memory cell adjacent to a drain select transistor, and
wherein the closer a word line group among the plurality of word line groups is to a source select transistor in the memory cell array, the greater a pre-bias voltage to be applied to word lines included in the word line group is.

10. The semiconductor memory device according to claim 9 , wherein a pre-bias voltage that is applied to word lines included in a word line group to which the selected word line belongs has a default value, and the pre-bias voltage that is applied to the plurality of word lines disposed between the word line group to which the selected word line belongs and the drain select transistor also has a default value.

11. The semiconductor memory device according to claim 9 ,
wherein the control logic determines a precharge voltage to be applied to a common source line based on a position of the selected word line, and
wherein the control logic controls the peripheral circuit such that the closer the selected word line is to the drain select transistor, the greater the precharge voltage to be applied to the common source line is.

12. An operating method of a semiconductor memory device, comprising:
applying pre-bias voltages to a plurality of word lines, respectively; and
applying a program voltage to a selected word line among the plurality of word lines after the pre-bias voltages are applied to the plurality of word lines,
wherein the plurality of word lines are grouped into a plurality of word line groups based on positions of the plurality of word lines, and
wherein the pre-bias voltages are determined according to the plurality of word line groups.

13. The operating method according to claim 12 , wherein
the closer a word line group among the plurality of word line groups is to a first-programmed memory cell in a memory cell array, the lower a pre-bias voltage to be applied to word lines included in the word line group is.

14. The operating method according to claim 12 ,
wherein memory cells are programmed in a sequence from a memory cell adjacent to a source select transistor, and
wherein
the closer a word line group among the plurality of word line groups is to a drain select transistor in a memory cell array, the greater a pre-bias voltage to be applied to word lines included in the word line group is.

15. The operating method according to claim 14 ,
wherein each of the plurality of word line groups includes the same number of word lines.

16. The operating method according to claim 14 ,
wherein the closer the word line group among the plurality of word line groups is to the source select transistor in the memory cell array, the greater the number of word lines included in the word line group is.

17. The operating method according to claim 12 , the method further comprising:
applying a precharge voltage to be applied to a common source line such that the closer the selected word line is to a first-programmed memory cell in a memory cell array, the greater the precharge voltage to be applied to the common source line is.

18. The operating method according to claim 12 ,
wherein memory cells are programmed in a sequence from a memory cell adjacent to a drain select transistor, and
wherein the closer a word line group among the plurality of word line groups to a source select transistor in a memory cell array, the greater a pre-bias voltage to be applied to word lines included in the word line group is.

19. The operating method according to claim 18 , the method further comprising:
applying a precharge voltage to be applied to a common source line such that the closer the selected word line is to the drain select transistor, the greater the precharge voltage to be applied to the common source line is.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C29/34

  Accessing multiple bits simultaneously · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title