Offload processing of data packets containing financial market data

Patent metadata

Field	Value
Publication number	US-10121196-B2
Application number	US-201313833098-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 27, 2012
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Various techniques are disclosed for offloading the processing of data packets that contain financial market data. For example, incoming data packets can be processed through an offload processor to generate a new stream of outgoing data packets that organize financial market data in a manner different than the incoming data packets. Furthermore, in an exemplary embodiment, the offloaded processing can be resident in an intelligent switch, such as an intelligent switch upstream or downstream from an electronic trading platform.

First claim

What is claimed is:

1. An intelligent packet switch for reducing data processing latency at a packet destination by embedding data processing operations that would conventionally be performed at the packet destination into the intelligent packet switch, the switch comprising:
a plurality of ports;
switching logic; and
a processor, wherein the processor comprises at least one member of the group consisting of a reconfigurable logic device, a graphics processor unit (GPU), and a chip multi-processor (CMP);
wherein the switching logic and processor are co-resident within the intelligent switch;
at least one of the ports being configured to receive a plurality of incoming data packets, the incoming data packets comprising a plurality of financial market data messages, the financial market data messages comprising data that describes financial market data for a plurality of financial instruments;
at least another of the ports being configured to output a plurality of outgoing data packets, the outgoing data packets comprising data that describes at least a portion of the financial market data;
wherein the switching logic is configured to determine a port for the outgoing data packets with reference to the incoming data packets; and
wherein the at least one member is configured to perform a packet mapping operation on at least a portion of the data describing the financial market data; and
wherein, as part of the packet mapping operation for each of a plurality of the received incoming data packets, the at least one member is further configured to (1) determine a financial market data feed associated with a received incoming data packet, (2) access metadata associated with the determined financial market data feed, the metadata comprising data for enabling a parsing of that received incoming data packet, and (3) associate the accessed metadata with that received incoming data packet.

2. The switch of claim 1 wherein the parsing enabling data comprises a packet parsing template.

3. The switch of claim 2 wherein the at least one member is further configured to determine the financial market data feeds associated with the received incoming data packets according to a mapping to the metadata based on a tuple drawn from the received incoming data packets, the tuple comprising at least two members of the group consisting of an IP source address, a destination address, a protocol identifier, a source port number, and a destination port number for the received incoming data packets.

4. The switch of claim 3 wherein the at least one member is further configured to perform the mapping via a hash table based on the tuple.

5. The switch of claim 2 wherein the accessed metadata further comprises a financial market data message parsing template.

6. The switch of claim 5 wherein the accessed metadata further comprises a pre-normalization template for financial market data within the financial market data messages.

7. The switch of claim 5 wherein the accessed metadata further comprises at least one member of the group consisting of (1) a market identification code (MIC), (2) a data source identification code (DSIC), (3) a line identification code (LIC), and (4) a flag for identifying whether the determined financial market data feed employs FIX/FAST encoding.

8. The switch of claim 1 wherein the switch is resident in a data distribution network upstream from a trading platform for financial instruments.

9. An intelligent packet switch for reducing data processing latency at a packet destination by embedding data processing operations that would conventionally be performed at the packet destination into the intelligent packet switch, the switch comprising:
a plurality of ports;
switching logic; and
a processor, wherein the processor comprises at least one member of the group consisting of a reconfigurable logic device, a graphics processor unit (GPU), and a chip multi-processor (CMP);
wherein the switching logic and processor are co-resident within the intelligent switch;
at least one of the ports being configured to receive a plurality of incoming data packets, the incoming data packets comprising a plurality of financial market data messages, the financial market data messages comprising data that describes financial market data for a plurality of financial instruments, wherein a plurality of the received incoming data packets correspond to a plurality of financial market data feeds such that a plurality of the received incoming data packets are feed-specific incoming data packets, each of a plurality of the feed-specific incoming data packets comprising a plurality of financial market data messages from the same financial market data feed;
at least another of the ports being configured to output a plurality of outgoing data packets, the outgoing data packets comprising data that describes at least a portion of the financial market data;
wherein the switching logic is configured to determine a port for the outgoing data packets with reference to the incoming data packets; and
wherein the at least one member is configured to perform a repackaging operation on at least a portion of the data describing the financial market data;
wherein, as part of the repackaging operation, the at least one member is further configured to (1) process the received incoming data packets to depacketize the financial market data messages, (2) process the financial market data of the depacketized financial market data messages to select financial market data according to a criterion, and (3) packetize the selected financial market data to generate a plurality of the outgoing data packets for output via the at least another port, the outgoing data packets comprising criterion-specific outgoing data packets, each criterion-specific outgoing data packet comprising selected financial market data that shares the same criterion, and wherein a plurality of the criterion-specific outgoing data packets group financial market data therein from a plurality of different financial market data feeds.

10. The switch of claim 9 wherein the switching logic is resident on the processor.

11. The switch of claim 10 wherein the processor comprises a field programmable gate array (FPGA).

12. The switch of claim 11 wherein the processor further comprises another FPGA, and wherein the switching logic is resident on an FPGA of the switch.

13. The switch of claim 12 wherein the FPGAs are configured to communicate with each other via a custom interface.

14. The switch of claim 12 wherein the FPGAs are configured to communicate with each other via a PCI-express interface.

15. The switch of claim 12 wherein the FPGAs are configured to communicate with each other via a XAUI interface.

16. The switch of claim 12 wherein the FPGAs are configured to communicate with each other via an Ethernet interface.

17. The switch of claim 9 wherein the switching logic is resident on an application specific integrated circuit (ASIC).

18. The switch of claim 17 wherein the processor is resident on a field programmable gate array (FPGA), wherein the ASIC and the FPGA are configured to communicate with each other via a custom interface.

19. The switch of claim 17 wherein the processor is resident on a field programmable gate array (FPGA), wherein the ASIC and the FPGA are configured to communicate with each other via a PCI-express interface.

20. The switch of claim 17 wherein the processor is resident on a field programmable gate array (FPGA), wherein the ASIC and the FPGA are con

Assignees

• Ip Reservoir Llc

Inventors

• Parsons Scott
• Taylor David E
• Indeck Ronald S

Classifications

• G06Q40/04 Primary

  Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange · CPC title