Host-safe firmware upgrade of a PCI express device

Patent metadata

Field	Value
Publication number	US-10120823-B2
Application number	US-201514866087-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence. In one embodiment, the peripheral device is a Non-Volatile Memory Express (NVMe)-compliant data storage device.

First claim

What is claimed is:

1. A method of upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device, the method comprising:
halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence comprising performing processes necessary for the peripheral device to shut down;
resetting the peripheral device after a predetermined time period of completion of the shutdown sequence;
initializing the firmware stored in a persistent storage location of the peripheral device;
re-establishing a connection between the peripheral device and the host device through a link negotiation setting a link width and link speed of the PCIe bus;
transferring the firmware from the host device to a buffer storage location of the peripheral device;
loading the firmware from the buffer storage location to the persistent storage location of the peripheral device;
setting a state of the peripheral device to a pending update state once the firmware is loaded to the persistent storage location of the peripheral device; and
beginning the predetermined time period after detecting both the peripheral device has completed the shutdown sequence and the pending update state of the peripheral device is set.

2. The method of claim 1 , further comprising polling a status of the peripheral device to detect the peripheral device has completed the shutdown sequence.

3. The method of claim 2 , wherein polling the status of the peripheral device comprises reading a register of the peripheral device corresponding to either an active or a shutdown state of the peripheral device.

4. The method of claim 1 , further comprising initiating the shutdown sequence after the firmware is loaded to the persistent storage location of the peripheral device.

5. The method of claim 1 , further comprising selecting the predetermined time period to be greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.

6. The method of claim 1 , wherein the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.

7. The method of claim 1 , wherein the predetermined time period is between 1 ms and 200 ms.

8. The method of claim 1 , wherein the peripheral device is a data storage device.

9. The method of claim 1 , wherein the peripheral device is a Non-Volatile Memory Express (NVMe)-compliant data storage device.

10. The method of claim 9 , wherein the NVMe-compliant data storage device is a Solid State Drive (SSD).

11. The method of claim 9 , wherein the shutdown sequence includes disabling one or more NVMe command queues and performing a Flash Translation Layer (FTL) flush.

12. A computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device by performing:
halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence comprising performing processes necessary for the peripheral device to shut down;
resetting the peripheral device after a predetermined time period after completion of the shutdown sequence;
initializing the firmware stored in a persistent storage location of the peripheral device; and
re-establishing a connection between the peripheral device and the host device through a link negotiation setting a link width and link speed of the PCIe bus;
transferring the firmware from the host device to a buffer storage location of the peripheral device;
loading the firmware from the buffer storage location to the persistent storage location of the peripheral device;
setting a state of the peripheral device to a pending update state once the firmware is loaded to the persistent storage location of the peripheral device; and
beginning the predetermined time period after detecting both the peripheral device has completed the shutdown sequence and the pending update state of the peripheral device is set.

13. The computer readable medium of claim 12 , further comprising instructions for performing:
polling a status of the peripheral device to detect the peripheral device has completed the shutdown sequence.

14. The computer readable medium of claim 12 , further comprising instructions for performing: initiating the shutdown sequence after the firmware is loaded to the persistent storage location of the peripheral device.

15. The computer readable medium of claim 12 , further comprising instructions for performing:
selecting the predetermined time period to be greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.

16. The computer readable medium of claim 12 , wherein the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.

17. The computer readable medium of claim 12 , wherein the predetermined time period is between 1 ms and 200 ms.

18. The computer readable medium of claim 12 , wherein the peripheral device is a data storage device.

19. The computer readable medium of claim 12 , wherein the peripheral device is a Non-Volatile Memory Express (NVMe)-compliant data storage device.

20. The computer readable medium of claim 19 , wherein the NVMe-compliant data storage device is a Solid State Drive (SSD).

21. The computer readable medium of claim 19 , wherein the shutdown sequence includes disabling one or more NVMe command queues and performing a Flash Translation Layer (FTL) flush.

Assignees

• Toshiba Memory Corp

Inventors

• Waidhofer Gordon W
• Aiouaz Ali
• Delaney Christopher
• Thompson Leland

Classifications

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F8/654

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/4403

  Processor initialisation · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title