Techniques for detecting race conditions

Patent metadata

Field	Value
Publication number	US-10120781-B2
Application number	US-201315026515-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Dec 12, 2013
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A computer-implemented method for detecting race conditions comprising:
detecting a cache event associated with a race condition between accesses to a piece of data by at least one application routine executed by a processor component, the cache event comprising a read-for-ownership (RFO) cache event or a hit-modified (HITM) cache event based on a cache coherency mechanism;
recurringly capturing an indication of a state of the processor component as monitoring data in response to an occurrence of the cache event at a selected interval of multiple occurrences of the cache event, each instance of the indication of the state comprising an address of an instruction pointer of the processor component and a type of the cache event indicating whether the cache event is a RFO cache event or a HITM cache event;
determining whether the race condition is a read operation of a first portion of the application routine and a write operation of a second portion of the at least one application routine based on an identifier of at least one of the first portion, the second portion, a core of the processor component that executes one of the first and second portions, or a thread of execution of one of the first and second portions; and

removing the indication from the monitoring data based on the cache event not arising from the race condition between the read operation of the first portion of the application routine and the write operation of a second portion of the application routine to generate a reduced data comprising a subset of multiple indications of the state of the processor component of the monitoring data.

2. The computer-implemented method of claim 1 , comprising transmitting the reduced data to a debugging device via a network.

3. The computer-implemented method of claim 1 , the race condition comprising a race condition between a first write operation of the application routine executed by the processor component in a first thread of execution to write to the piece of data, and a second write operation of another application routine executed by the processor component in a second thread of execution to write to the piece of data.

4. The computer-implemented method of claim 1 , wherein each instance of the indication of the state comprises an identifier of a core to enable debugging.

5. An apparatus to detect race conditions comprising:
a hardware processor component, comprising a monitoring unit;
a trigger component stored in a memory which when executed by the processor component causes the monitoring unit to detect a cache event arising from a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event, the cache event comprising a read-for-ownership (RFO) cache event or a hit-modified (HITM) cache event based on a cache coherency mechanism, and the indication of the state comprising an address of an instruction pointer of the processor component, a type of the cache event indicating whether the cache event is a RFO cache event or a HITM cache event, and an identifier of a core to enable debugging;
a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event; and
a filter component for execution by the processor component to:
determine whether the race condition is between a first access to the piece of data by a first portion of an application routine executed by the processor component and a second access to the piece of data by a second portion of the application routine based on an identifier of at least one of the first portion, the second portion, a core of the processor component that executes one of the first and second portions, or a thread of execution of one of the first and second portions, and

remove the indication from the monitoring data based on the cache event not arising from the race condition between the first access to the piece of data by the first portion of the application routine executed by the processor component and the second access to the piece of data by the second portion of the application routine to generate reduced data comprising a subset of multiple indications of the state of the processor component of the monitoring data.

6. The apparatus of claim 5 , the trigger component to dynamically enable the capture of the indication based on whether an application routine comprising multiple portions for concurrent execution by the processor component is currently executed by the processor component.

7. The apparatus of claim 5 , wherein the first access comprising a write operation and the second access comprising one of a read operation and a write operation.

8. The apparatus of claim 5 , the race condition comprising a race condition between a read operation of a first application routine executed by the processor component in a first thread of execution to read the piece of data, and a write operation of a second application routine executed by the processor component in a second thread of execution to write to the piece of data.

9. An apparatus to detect race conditions comprising:
a first hardware processor component;
a second hardware processor component;
a trigger component stored in a memory which when executed by the processor components configure a monitoring unit of the first hardware processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture a first indication of a state of the first hardware processor component as a first monitoring data in response to an occurrence of the cache event, and to configure a monitoring unit of the second hardware processor component to detect the cache event and to capture a second indication of a state of the second hardware processor component as a second monitoring data in response to an occurrence of the cache event, the cache event comprising a read-for-ownership (RFO) cache event or a hit-modified (HITM) cache event based on a cache coherency mechanism; and
a filter component to:
determine whether the race condition is between first and second portions of an application routine based on an identifier of at least one of the first portion, the second portion, a core of the first hardware processor component that executes one of the first and second portions, a core of the second hardware processor component that executes one of the first and second portions, or a thread of execution of one of the first and second portions, and

remove at least one of the first indication and the second indication in a reduced data based on the cache event not arising from the race condition between access to the piece of data by the first portion of an application routine executed by one of the first and second hardware processor components and the access to the piece of data by the second portion of the application routine executed by one of the first and second hardware processor components.

10. The apparatus of claim 9 , the trigger component to dynamically enable the capture of the first indication and the second indication based on whether an application routine comprising multiple portions for concurrent execution by at least one of the first hardware processor component and the second hardware processor component is currently executed by at least one of the first hardware processor component and the second hardware processor component.

11. The apparatus of claim 9 , comprising a counter component to confi

Assignees

• Intel Corp

Inventors

• Hu Shiliang
• Pokam Gilles A
• Pereira Cristiano L
• Gottschlich Justin E

Classifications

• G06F11/3632 Primary

  of specific synchronisation aspects · CPC title

• G06F9/526

  Mutual exclusion algorithms · CPC title

• G06F11/30

  Monitoring · CPC title

• G06F11/0715

  in a system implementing multitasking (multitasking per se G06F9/46) · CPC title

• G06F11/28

  by checking the correct order of processing (G06F11/08 - G06F11/26 take precedence; monitoring patterns of pulse trains H03K5/19) · CPC title