Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor using null internal operations (IOPs)

Patent metadata

Field	Value
Publication number	US-10120683-B2
Application number	US-201615139430-A
Country	US
Kind code	B2
Filing date	Apr 27, 2016
Priority date	Apr 27, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor with null internal operations (IOPs) includes: receiving an IOP with an even ITAG requirement; determining that the IOP is to be assigned an odd ITAG; and inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

First claim

What is claimed is:

1. A method for supporting even instruction tag (‘ITAG’) requirements with null internal operations (IOPs), the method comprising:
receiving an IOP with an even ITAG requirement, wherein the even ITAG requirement is a requirement that the IOP is assigned an even ITAG;
determining that the IOP is to be assigned an odd ITAG; and
inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

2. The method of claim 1 wherein determining that the IOP is to be assigned an odd ITAG comprises:
determining, during a previous cycle, that the ITAG assigning unit will assign the IOP an odd ITAG based on a sequential assignment of ITAGs.

3. The method of claim 1 wherein the IOP is grouped with a companion IOP, and the IOP is received before the companion IOP, and wherein the companion IOP is assigned a subsequent odd ITAG.

4. The method of claim 3 further comprising:
sending the IOP to a first execution slice; and
sending the companion IOP to a second execution slice.

5. The method of claim 4 wherein the first execution slice calculates a subsequent odd ITAG assigned to the companion IOP based on the even ITAG assigned to the IOP.

6. The method of claim 3 wherein the IOP and the companion IOP are each part of a single instruction.

7. The method of claim 1 further comprising:
sending the null IOP to a completion unit.

8. A multi-slice computer processor for supporting even instruction tag (‘ITAG’) requirements with null internal operations (IOPs), the multi-slice computer processor comprising null IOP insertion logic configured to carry out the steps of:
receiving an IOP with an even ITAG requirement, wherein the even ITAG requirement is a requirement that the IOP is assigned an even ITAG;
determining that the IOP is to be assigned an odd ITAG; and
inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

9. The multi-slice computer processor of claim 8 wherein determining that the IOP is to be assigned an odd ITAG comprises:
determining, during a previous cycle, that the ITAG assigning unit will assign the IOP an odd ITAG based on a sequential assignment of ITAGs.

10. The multi-slice computer processor of claim 8 wherein the IOP is grouped with a companion IOP, and the IOP is received before the companion IOP, and wherein the companion IOP is assigned a subsequent odd ITAG.

11. The multi-slice computer processor of claim 10 further configured for:
sending the IOP to a first execution slice; and
sending the companion IOP to a second execution slice.

12. The multi-slice computer processor of claim 11 wherein the first execution slice calculates a subsequent odd ITAG assigned to the companion IOP based on the even ITAG assigned to the IOP.

13. The multi-slice computer processor of claim 10 wherein the IOP and the companion IOP are each part of a single instruction.

14. The multi-slice computer processor of claim 8 further configured for:
sending the null IOP to a completion unit.

15. A computing system including a multi-slice computer processor configured for supporting even instruction tag (‘ITAG’) requirements with null internal operations (IOPs), the multi-slice computer processor comprising null IOP insertion logic configured to carry out the steps of:
receiving an IOP with an even ITAG requirement, wherein the even ITAG requirement is a requirement that the IOP is assigned an even ITAG;
determining that the IOP is to be assigned an odd ITAG; and
inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

16. The computing system of claim 15 wherein determining that the IOP is to be assigned an odd ITAG comprises:
determining, during a previous cycle, that the ITAG assigning unit will assign the IOP an odd ITAG based on a sequential assignment of ITAGs.

17. The computing system of claim 15 wherein the IOP is grouped with a companion IOP, and the IOP is received before the companion IOP, and wherein the companion IOP is assigned a subsequent odd ITAG.

18. The computing system of claim 17 , wherein the multi-slice computer processor further configured to carry out:
sending the IOP to a first execution slice; and
sending the companion IOP to a second execution slice.

19. The computing system of claim 18 wherein the first execution slice calculates a subsequent odd ITAG assigned to the companion IOP based on the even ITAG assigned to the IOP.

20. The computing system of claim 15 , wherein the multi-slice computer processor further configured to carry out:
sending the null TOP to a completion unit.

Assignees

• IBM

Inventors

• Carlough Steven R
• Feiste Kurt A
• Kennedy Paul M
• Williams Phillip G

Classifications

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F15/8069

  using a cache · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title