Persistent memory descriptor

Patent metadata

Field	Value
Publication number	US-10120600-B2
Application number	US-201715728936-A
Country	US
Kind code	B2
Filing date	Oct 10, 2017
Priority date	Dec 8, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.

First claim

What is claimed is:

1. A memory controller comprising:
a processing unit configured to generate descriptor fields for memory operations occurring between a volatile memory and a persistent memory coupled to the memory controller, wherein each descriptor field corresponds to a segment of source data in the volatile memory and stores an address of the corresponding segment, the processing unit to store each segment of the source data with the corresponding descriptor field as backup data in the persistent memory and to read the backup data from the persistent memory and determine the corresponding address of each segment in the volatile memory from the corresponding descriptor field.

2. The memory controller of claim 1 , wherein each descriptor field further comprises version control information.

3. The memory controller of claim 1 , wherein each descriptor field further comprises error correction information.

4. The memory controller of claim 1 , wherein the volatile memory comprises one or more dynamic random access memory (DRAM) modules.

5. The memory controller of claim 1 , wherein the persistent memory comprises one or more flash memory modules.

6. The memory controller of claim 1 , wherein to read the backup data from the persistent memory, the processing unit to read one or more segments non-sequentially.

7. The memory controller of claim 6 , wherein the processing unit is configured to restore the one or more segments from the persistent memory to the corresponding addresses in the volatile memory based on information stored in the corresponding descriptor fields in the backup data.

8. The memory controller of claim 7 , wherein the processing unit is configured to write the one or more segments to the corresponding addresses in the volatile memory without waiting until the one or more segments are sequentially aligned.

9. A method comprising:
initiating, by a memory controller, a save operation to copy one or more segments of source data in a volatile memory to a persistent memory;
generating a descriptor field corresponding to each segment of the source data, wherein each descriptor field stores an address of the corresponding segment in the volatile memory;
storing the one or more segments of the source data with the corresponding descriptor fields as backup data in the persistent memory; and
reading the backup data from the persistent memory to determine the addresses of the one or more segments in the volatile memory from the corresponding descriptor fields.

10. The method of claim 9 , wherein each descriptor field further comprises version control information.

11. The method of claim 9 , wherein each descriptor field further comprises error correction information.

12. The method of claim 9 , wherein the volatile memory comprises one or more dynamic random access memory (DRAM) modules.

13. The method of claim 9 , wherein the persistent memory comprises one or more flash memory modules.

14. The method of claim 9 , wherein reading the backup data from the persistent memory comprises reading the one or more segments non-sequentially.

15. The method of claim 14 , further comprising:
initiating a restore operation to copy the one or more segments from the persistent memory to the corresponding addresses in the volatile memory based on information stored in the corresponding descriptor fields in the backup data.

16. The method of claim 15 , further comprising:
writing the one or more segments to the corresponding addresses in the volatile memory without waiting until the one or more segments are sequentially aligned.

17. A memory controller comprising:
a processing unit configured to generate descriptor fields for memory operations occurring between a dynamic random access memory (DRAM) module and a flash memory module coupled to the memory controller, wherein each descriptor field corresponds to a segment of source data in the DRAM module and stores an address of the corresponding segment, the processing unit to store each segment of the source data with the descriptor field as backup data in the flash memory module and to read the backup data from the flash memory module and determine the corresponding address of each segment in the DRAM module from the descriptor field.

18. The memory controller of claim 17 , wherein each descriptor field further comprises version control information.

19. The memory controller of claim 17 , wherein each descriptor field further comprises error correction information.

20. The memory controller of claim 17 , wherein the processing unit is configured to restore one or more non-sequential segments from the flash memory module to the corresponding addresses in the volatile memory based on information stored in the corresponding descriptor fields in the backup data without waiting until the one or more segments are sequentially aligned.

Assignees

• Rambus Inc

Inventors

• Shallal Aws
• Williams Collins
• Kunkel Dan
• Wolf William

Classifications

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F3/0608

  Saving storage space on storage systems · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/1446

  Point-in-time backing up or restoration of persistent data · CPC title

• G06F2212/60

  Details of cache memory · CPC title