In-band beating removal for a MEMS gyroscope

Patent metadata

Field	Value
Publication number	US-10119822-B2
Application number	US-201315035869-A
Country	US
Kind code	B2
Filing date	Nov 22, 2013
Priority date	Nov 22, 2013
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Vibration gyroscope circuitry, connectable to a vibrating MEMS gyroscope, includes drive circuitry for driving the gyroscope and a measurement circuit for providing a drive measurement signal indicating displacement of a mass along a drive axis. Sense circuitry processes a sense measurement signal of the gyroscope indicating displacement of the mass along a sense axis. A digital sample clock generator includes an oscillator for generating a master clock, a counter for counting master clock periods during one period of an input signal derived from the drive measurement signal, and a number count monitor for determining during how many input signal periods the number count stays constant and for comparing a number of constant periods with a critical number of constant periods. A frequency shifter triggers the oscillator to shift the master clock frequency whenever the monitor determines that the number of constant periods exceeds the critical number of constant periods.

First claim

The invention claimed is:

1. A vibration gyroscope circuitry (VCIRC) connectable to a vibrating MEMS (micro-electro-mechanical-system) gyroscope (VMEMS), the circuitry comprising:
a drive circuitry (DRIVE) arranged to drive, when said vibration gyroscope circuitry (VCIRC) is connected, the vibrating MEMS gyroscope (VMEMS) and comprising a drive measurement circuit (DMU) arranged to provide a drive measurement voltage signal (DMV) forming a measure of a displacement of a gyroscope mass (M) along a drive axis; and
a sense circuitry (SENSE) is arranged to, when said vibration gyroscope circuitry (VCIRC) is connected, process a sense measurement signal of the vibrating MEMS gyroscope (VMEMS) forming a measure for a displacement of said gyroscope mass (M) along a sense axis when said gyroscope mass (M) is being displaced along the drive axis by the drive circuitry, wherein the displacement of the gyroscope mass (M) along the sense axis occurs in the presence of angular rotation;
wherein the drive circuitry (DRIVE) further comprises a digital sample clock generator (SCG) for generating a sample clock signal (SCLK) from an input signal (FDxy) derivable from the drive measurement voltage signal (DMV), the sample clock generator (SCG) comprising:
an oscillator (HFOSC) arranged to generate a master clock (MOSC) with a master clock period (MOSC_PER) and a master clock frequency (F clk ), the oscillator being arranged to shift the master clock frequency;
a synchronization circuit (SYN) arranged to detect a start of an input signal period (FD_PER) of the input signal (FDxy) and to, upon detecting the start, generate a synchronization pulse (FD_OSC) in synchronization with the master clock (MOSC);
a counter (OSCCNTR) arranged to count master clock periods (MOSC_PER) between the synchronization pulse (FD_OSC) and a subsequent synchronization pulse (FD_OSC′) to obtain a number of the master clock periods (MOSC_PER) between the synchronization pulse (FD_OSC) and the subsequent synchronization pulse (FD_OSC′) as a number count (CNT);
a multiplier (MULT) arranged to multiply the number count with a pre-determined phase shift fraction (PhPerc) to obtain a number of trim periods (TRM);
a delay circuit (DLY) arranged to generate the sample clock signal (SLCK) with a clock signal period (SCLK_PER) corresponding to the number count (CNT) and with a delay relative to the synchronization pulse corresponding to the number of trim periods (TRM);
a number count monitor (NCM) arranged to determine during how many input signal periods the number count stays constant, to obtain a number of constant periods (N cp ), and to compare the number of constant periods (N cp ) with a critical number of constant periods (N cp _ crit ); and
a frequency shifter (FSH) arranged to trigger said oscillator to shift the master clock frequency whenever the number count monitor (NCM) has determined that the number of constant periods (N cp ) exceeds the critical number of constant periods (N cp _ crit ).

2. The vibration gyroscope circuitry (VCIRC) according to claim 1 , the oscillator (HFOSC) being arranged to generate four predefined master clock frequencies.

3. The vibration gyroscope circuitry (VCIRC) according to claim 1 , the pre-determined phase shift fraction (PhPerc) being 0.25.

4. The vibration gyroscope circuitry (VCIRC) according to claim 1 , the master clock frequency being in a range of 50-1000 times the frequency of the input signal (FDxy).

5. The vibration gyroscope circuitry (VCIRC) according to claim 1 , the frequency of the input signal (FDxy) being in a range of 1 kHz 100 kHz.

6. The vibration gyroscope circuitry (VCIRC) according to claim 1 , wherein the drive circuitry (DRIVE) further comprises a first capacitance-to-voltage circuit (C2V 1 ), and a threshold detector (ThrM); and wherein:
the first capacitance-to-voltage circuit (C2V 1 ) is arranged to provide the drive measurement voltage signal (DMV) indicative of the displacement of the gyroscope mass (M) along the drive axis (x) of the vibrating MEMS gyroscope (VMEMS);
the threshold detector (ThrM) is arranged to perform a threshold detection on the drive measurement voltage signal (DMV) to obtain the input signal as a digital signal (FDxy); and
the digital sample clock generator (SCG) is arranged to receive the digital signal (FDxy) and to generate the sample clock in dependence on a pre-determined in-phase phase shift fraction (PhI) as an in-phase sample clock (ICLK) so as to obtain the in-phase sample clock in-phase with the drive measurement voltage signal (DMV).

7. The vibration gyroscope circuitry (VCIRC) according to claim 6 , wherein the drive circuitry (DRIVE) further comprises a peak detector (PkD), a subtractor (SUB), an integrator (INT) and a variable gain amplifier (VGA);
the peak detector (PkD) being arranged to detect a peak of the drive measurement voltage signal (DMV) to obtain a peak value;
the subtractor (SUB) being arranged to subtract the peak value from a pre-determined reference envelope amplitude (AGC_ref) to obtain a gain factor (VGA_ctrl);
the integrator (INT) being arranged to integrate the drive measurement voltage signal (DMV) to obtain an integrated drive measurement voltage signal (DMI); and
the variable gain amplifier (VGA) being arranged to amplify the integrated drive measurement voltage signal (DMI) with the gain factor to obtain a drive actuation voltage signal (DAS) and to provide the drive actuation voltage signal (DAS) to a drive actuation circuit (DAS) of the vibration MEMS gyroscope (VMEMS).

8. The vibration gyroscope circuitry (VCIRC) according to claim 7 , wherein the sense circuitry (SENSE) further comprises a sampler (IMOD), a second capacitance-to-voltage circuit (C2V 2 ), a low pass filter (LPF) and an analogue-digital converter (ADC);
the second capacitance-to-voltage unit (C2V 2 ) being arranged to provide a sense measurement voltage signal (SMV) indicative of the displacement of the gyroscope mass (M) along the sense axis (y), the sense axis (y) being at a sense angle relative to the drive axis (x);
the sampler (IMOD) being arranged to sample the sense measurement voltage signal (SMV) with the in-phase sample clock (ICLK) to obtain in-phase sense sample values;
the low pass filter being arranged to filter the in-phase sense sample values, to obtain filtered in-phase sense sample values; and
the analogue-digital-converter (ADC) being arranged to convert the filtered in-phase sense sample values from analogue values to digital values representing a measure of an angular rate.

9. The vibration gyroscope circuitry (VCIRC) according to claim 8 , the low pass filter having a cut of frequency in a range of 100-400 kHz.

10. A method of generating a sample clock signal (SCLK) from an input signal (FD), the method comprising:
generating a master clock (MOSC) with a master clock period;
generating a synchronization pulse (FD_OSC) from detecting a start of an input signal period (FD_PER) of the input signal (FD) and, upon detecting the start, generating the synchronization pulse (FD_OSC) in synchronization with the master clock (MOSC);
counting master clock periods between subsequent synchronization pulses to obtain the number of the master clock periods between the subsequent synchronization pulses as a number count;
determining a number of trim periods from multiplying the number count with a pre-determined phase shift fraction (PhPerc);
generating the sample clock signal (SLCK) with a clock signal period (SCLK_PER) as an in-phase sample clock corresponding to the number count (CNT) and with a delay relative to the synchronization pulse corresponding to the number of trim periods (TRM);
determining during how many input s

Assignees

• Cassagnes Thierry
• Beaulaton Hugues
• Cornibert Laurent
• Teo Yean Ling
• Nxp Usa Inc

Inventors

• Cassagnes Thierry
• Beaulaton Hugues
• Cornibert Laurent
• Teo Yean Ling

Classifications

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/1694

  the I/O peripheral being a single or a set of motion sensors for pointer control or gesture input obtained by sensing movements of the portable computer · CPC title

• G01C19/04

  Details · CPC title

• H04L7/06

  the synchronisation signals differing from the information signals in amplitude, polarity or frequency {or length} · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title