Hardware protocol stack with user-defined protocol applied thereto and method for applying user-defined protocol to hardware protocol stack

US10116774B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10116774-B2
Application numberUS-201615388109-A
CountryUS
Kind codeB2
Filing dateDec 22, 2016
Priority dateApr 26, 2016
Publication dateOct 30, 2018
Grant dateOct 30, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to a hardware protocol stack, and more particularly, to a hardware protocol stack to which a user-defined protocol is applicable. The present disclosure compares header information stored in a register unit with header information of a received frame, and determines a processing of the received frame on the basis of a comparison result. Also, according to a determined frame process method, data of the received frame is processed based on a logic according to the header information, it is stored at a designated position, or a response frame is transmitted.

First claim

Opening claim text (preview).

What is claimed is: 1. A hardware protocol stack to which a user-defined protocol is applied, comprising: a register unit in which header information is stored; a comparison unit configured to compare header information of a received frame with the header information stored in the register unit to determine whether the header information is matched to the other; an interface logic unit configured to determine a process of the received frame on the basis of a comparison result of the comparison unit; and a logic process unit configured to process data of the received frame based on a logic according to the header information when the frame process method, which is determined in the interface logic according to the header information stored in the register unit and being matched to the header information of the received frame, is a processing of a frame, wherein the logic according to the header information includes a unit designation of the data according to the header information; wherein the unit designation of the data is performed such that the logic process unit sets a basic offset and a size unit of the data when receiving a request for writing payload data in a specific region of the data and then stores payload in the basic offset by expanding the payload to be corresponded to the set size unit of the data. 2. The hardware protocol stack of claim 1 , further comprising: a frame receiving unit configured to store the received frame in a predesignated position when the frame process method, which is determined in the interface logic unit according to the header information stored in the register unit and matched to the header information of the received frame, is a storing of a frame. 3. The hardware protocol stack of claim 1 , further comprising: a frame production unit configured to produce and transmit a response frame with respect to the received frame when the frame process method, which is determined in the interface logic unit according to the header information stored in the register unit and matched to the header information of the received frame, is a transmitting of a response frame. 4. A method for applying a user-defined protocol to a hardware protocol stack, comprising: receiving an input of a register in which at least one or more frame header information is included from a user in a register unit; comparing frame header information of a received frame with at least one or more register header information in a comparison unit; determining a frame process method on the basis of register header information matched to the at least one or more frame header information among the at least one or more register header information in an interface logic unit; and processing, by a logic process unit, data of the received frame based on a logic according to the header information when the frame process method, which is determined in the interface logic unit, is a processing of a frame, wherein the logic according to the header information includes a unit designation of the data according to the header information, wherein the unit designation of the data is performed such that the logic process unit sets a basic offset and a size unit of the data when receiving a request for writing payload data in a specific region of the data and then stores payload in the basic offset by expanding the payload to be corresponded to the set size unit of the data. 5. The method of claim 4 , further comprising: producing and transmitting a response frame with respect to the received frame in a frame production unit when the frame process method, which is determined in the interface logic unit, is a transmitting of a response frame; and storing the received frame at a preset destination in a frame receiving unit when the frame process method, which is determined in the interface logic unit, is a storing of a frame.

Assignees

Inventors

Classifications

  • Definitions, standards or architectural aspects of layered protocol stacks · CPC title

  • Special purpose or proprietary protocols or architectures (network applications for proprietary or special purpose networking environments H04L67/12) · CPC title

  • H04L69/22Primary

    Parsing or analysis of headers · CPC title

  • Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1] · CPC title

  • H04L69/03Primary

    Protocol definition or specification  (protocol conformance testing H04L1/244) · CPC title

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What does patent US10116774B2 cover?
The present disclosure relates to a hardware protocol stack, and more particularly, to a hardware protocol stack to which a user-defined protocol is applicable. The present disclosure compares header information stored in a register unit with header information of a received frame, and determines a processing of the received frame on the basis of a comparison result. Also, according to a determ…
Who is the assignee on this patent?
Lsis Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04L69/22. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 30 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).