Process-compensated HBT power amplifier bias circuits and methods

Patent metadata

Field	Value
Publication number	US-10116274-B2
Application number	US-201615216621-A
Country	US
Kind code	B2
Filing date	Jul 21, 2016
Priority date	Jun 14, 2012
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

First claim

What is claimed is:

1. A system for biasing a power amplifier, the system comprising:
a power amplifier circuit including a transistor, the transistor including a stack of layers formed on a semiconductor;
an integrated resistor formed as a layer stack device including a plurality of differently doped layers on the semiconductor that includes the transistor, the integrated resistor configured to sense a beta parameter of the power amplifier circuit, the beta parameter dependent on characteristics of the semiconductor and corresponding to a direct current gain; and
a biasing circuit configured to bias the transistor of the power amplifier circuit based at least in part on a measurement of the beta parameter sensed by the integrated resistor.

2. The system of claim 1 wherein the beta parameter is sensed based at least in part on a sheet resistance of the integrated resistor that corresponds to a measure of the beta parameter.

3. The system of claim 1 wherein the power amplifier circuit and the integrated resistor are on a first semiconductor die and the biasing circuit is on a second semiconductor die.

4. The system of claim 3 wherein the first semiconductor die is of a different material than the second semiconductor die.

5. The system of claim 1 wherein the integrated resistor is formed at least in part from at least one of the layers of the stack of layers of the transistor.

6. The system of claim 1 further comprising an isolation feature that isolates the integrated resistor from the transistor on the semiconductor.

7. The system of claim 1 wherein the biasing circuit is further configured to provide a reference current to the integrated resistor, the reference current having a value that depends on a resistance of the integrated resistor.

8. The system of claim 1 wherein the integrated resistor replaces a thin-film resistor within the power amplifier circuit.

9. A power amplifier module comprising:
a packaging substrate configured to support one or more circuit elements;
a power amplifier on the packaging substrate, the power amplifier including a transistor and an integrated resistor, the transistor including a stack of layers formed on a semiconductor, the integrated resistor being a layer stack device including a plurality of differently doped layers located on the semiconductor that includes the transistor, the integrated resistor configured to sense a beta parameter of the power amplifier, the beta parameter dependent on characteristics of the semiconductor and corresponding to a direct current gain; and
a biasing circuit configured to bias the transistor of the power amplifier based at least in part on a measurement of the beta parameter sensed by the integrated resistor.

10. The power amplifier module of claim 9 wherein the beta parameter is sensed based at least in part on a sheet resistance of the integrated resistor that corresponds to a measure of the beta parameter.

11. The power amplifier module of claim 9 wherein the power amplifier and the integrated resistor are on a first semiconductor die and the biasing circuit is on a second semiconductor die.

12. The power amplifier module of claim 11 wherein the first semiconductor die is of a different material than the second semiconductor die.

13. The power amplifier module of claim 9 wherein the integrated resistor is formed at least in part from at least one of the layers of the stack of layers of the transistor.

14. The power amplifier module of claim 9 wherein the power amplifier includes an isolation feature that isolates the integrated resistor from the transistor on the semiconductor.

15. The power amplifier module of claim 9 wherein the biasing circuit is further configured to provide a reference current to the integrated resistor, the reference current having a value that depends on a resistance of the integrated resistor.

16. The power amplifier module of claim 9 wherein the integrated resistor is configured to be sensitive to a change in one or more conditions associated with a layer of the stack of layers of the transistor.

17. A wireless device comprising:
a transceiver configured to process radio frequency signals;
an antenna in communication with the transceiver and configured to transmit an amplified radio frequency signal; and
a power amplifier module configured to amplify the signal, the power amplifier module including a power amplifier and a biasing circuit, the power amplifier including a transistor and an integrated resistor, the transistor including a stack of layers including a plurality of differently doped layers formed on a semiconductor, the integrated resistor being a layer stack device located on the semiconductor that includes the transistor, the integrated resistor configured to sense a beta parameter of the power amplifier, the beta parameter dependent on characteristics of the semiconductor and corresponding to a direct current gain, the biasing circuit configured to bias the transistor of the power amplifier based at least in part on a measurement of the beta parameter sensed by the integrated resistor.

18. The wireless device of claim 17 wherein the biasing circuit is further configured to provide a reference current to the integrated resistor, the reference current having a value that depends on a resistance of the integrated resistor.

19. The wireless device of claim 17 wherein the integrated resistor is configured to be sensitive to a change in one or more conditions associated with a layer of the stack of layers of the transistor.

Assignees

• Skyworks Solutions Inc

Inventors

• Ripley David Steven
• Lehtola Philip John
• Zampardi Jr Peter J
• Shao Hongxiao
• Ko Tin Myint
• Ozalas Matthew Thomas

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W42/265

  Shielding wires, e.g. constant potential wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/231

  Arrangements for applying bias · CPC title

• H10W44/206

  Wires · CPC title