Single-ended amplifier circuit with improved chopper configuration

Patent metadata

Field	Value
Publication number	US-10116267-B2
Application number	US-201715603004-A
Country	US
Kind code	B2
Filing date	May 23, 2017
Priority date	Nov 2, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

An amplifier circuit a differential input stage coupled to a first input and to a second input between which a differential input voltage is present. A converter stage is coupled to the input stage to convert the differential input voltage into a converted voltage. An output stage is coupled to the converter stage and generates, starting from the converted voltage, an output voltage on a single output of the amplifier circuit. A biasing stage is coupled to the input stage and to the output stage to supply a biasing current. A chopper module reduces a contribution of offset and noise associated with the output voltage. The chopper module is coupled to the input stage, converter stage, and to the biasing stage. The chopper module includes an input chopper stage, a converter chopper stage, and a biasing chopper stage that operate jointly under control of a chopper signal.

First claim

The invention claimed is:

1. An amplifier circuit, comprising:
an input stage, of a differential type, coupled to a first differential input and to a second differential input between which, in use, a differential input voltage is present;
a converter stage coupled to said input stage and configured to convert said differential input voltage into a single-ended converted voltage;
an output stage coupled to said converter stage and configured to generate, starting from said single-ended converted voltage, an output voltage on a single output;
a biasing stage, operatively coupled to said input stage and to said output stage for supplying a biasing current; and
a chopper module configured to reduce a contribution of offset and noise associated to said output voltage, wherein said chopper module includes:
an input chopper stage coupled to said input stage;
a converter chopper stage coupled to said converter stage and configured to generate said single-ended converted voltage; and
a biasing chopper stage coupled to said biasing stage and configured to generate said biasing current.

2. The amplifier circuit according to claim 1 , wherein said input chopper stage, said converter chopper stage, and said biasing chopper stage operate in combination in response to a chopper signal.

3. The amplifier circuit according to claim 1 , wherein said converter stage comprises: a current mirror formed by a first conversion transistor and a second conversion transistor having gate terminals connected together, wherein said first conversion transistor includes a drain terminal connected to a first internal node and said second conversion transistor includes a drain terminal connected to a second internal node.

4. The amplifier circuit of claim 3 , wherein said output stage comprises a first output transistor having a drain terminal connected to an output terminal on which said output voltage is present, and a gate terminal configured to receive said single-ended converted voltage.

5. The amplifier circuit of claim 4 , wherein said converter chopper stage further comprises a first chopper unit coupled between said first and second internal nodes and said gate terminals of said first and second conversion transistors, and wherein said first chopper unit is configured, responsive to a chopper signal having a first phase, to couple said first internal node to said gate terminals of said first and second conversion transistors and is configured, responsive to the chopper signal having a second phase, to couple said second internal node to said gate terminals of said first and second conversion transistors.

6. The amplifier circuit of claim 5 , wherein said converter chopper stage further comprises a second chopper unit coupled between said first and second internal nodes and said gate terminal of said first output transistor, and wherein said second chopper unit is configured, responsive to the chopper signal having the first phase, to couple said second internal node to said gate terminal of said first output transistor, and is configured, responsive to the chopper signal having the second phase, to couple said first internal node to said gate terminal of said first output transistor.

7. The amplifier circuit of claim 6 , wherein said biasing stage comprises a first biasing transistor and a second biasing transistor having gate terminals coupled together, and wherein said biasing chopper stage is coupled between the drain terminals of said first biasing transistor and said second biasing transistor and a first biasing node and a second biasing node, and wherein said biasing chopper stage is configured, responsive to the chopper signal having the first phase to couple said first biasing node and said second biasing node to said drain terminals of said first biasing transistor and said second biasing transistor, respectively, and is configured, responsive to the chopper signal having the second phase, to couple said first biasing node and said second biasing node to said drain terminals of said second biasing transistor and said first biasing transistor, respectively.

8. The amplifier circuit of claim 7 , wherein said first biasing transistor has a transconductance g m6 , said first and second conversion transistors have a transconductance of g m2,3 , said first output transistor has a transconductance of g m4 , and said second biasing transistor has a transconductance of g m7 , and wherein the relation among these transconductances is as follows:

g

m
⁢

⁢
6

2
·

g

m
⁢

⁢
2

,
3

·

g

m
⁢

⁢
4

=

g

m
⁢

⁢
7

.

9. The amplifier circuit of claim 8 , wherein said first and second biasing transistors are sized to have a same value of length and a same value of width, and wherein said first output transistor is sized to have a same value of length and a value of width that is twice a width of said first and second conversion transistors.

10. The amplifier circuit of claim 7 , wherein said input stage comprises a first input transistor and a second input transistor the first and second input transistors having respective source terminals connected together at the first biasing node and having respective drain terminals connected to said first internal node and said second internal node, respectively and wherein said input chopper stage is coupled between gate terminals of said first input transistor and second input transistor and said first differential input and second differential input, the input chopper stage configured, responsive to the chopper signal having the first phase, to couple said first differential input and second differential input to said gate terminals of said first input transistor and second input transistor, respectively, and configured, responsive to the chopper signal having the second phase, to couple said first differential input and second differential input to said gate terminals of said second input transistor and said first input transistor, respectively.

11. The amplifier circuit of claim 10 further comprising:
a capacitor element coupled between the gate terminal and the drain terminal of said first output transistor; and
a second output transistor connected to said drain terminal of said first output transistor and

Assignees

• St Microelectronics Srl

Inventors

• Polesel Stefano
• Nicollini Germano

Classifications

• H03F2203/45692

  the LC comprising one or more resistors in series with a capacitor coupled to the LC by feedback · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F3/387

  with semiconductor devices only · CPC title

• H03F3/45775

  by using cross switches · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title