Transformer without magnetic coupling, electromagnetic induction or mutual inductance

Patent metadata

Field	Value
Publication number	US-10116197-B2
Application number	US-201515509313-A
Country	US
Kind code	B2
Filing date	Oct 9, 2015
Priority date	Nov 5, 2014
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A front stage circuit of a transformer includes a switch series unit, capacitors, and a ground electrical path. The switch series unit, connected in parallel to a power supply, includes odd-numbered/even-numbered switches configured to be alternately turned ON. Assuming that mutual connection points of the switches and points at both ends of the switch series unit are m nodes in total, and one of the points at the both ends is a ground node, the capacitors are provided on at least one of a first electrical path that combines odd nodes and leads them to a first output port, and a second electrical path that combines even nodes and leads them to a second output port, and the capacitors are present to correspond to (m−1) nodes excluding the ground node. The ground electrical path connects the ground node directly to the first output port without an interposed capacitor.

First claim

The invention claimed is:

1. A transformer provided between a power supply and a load, and composed of a front stage circuit and a rear stage circuit, the transformer comprising:
the front stage circuit comprising,
a switch series unit composed of a plurality of switches, as many as a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the switch series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to the power supply,
under a condition that mutual connection points of the respective switches and points at the both ends of the switch series unit are nodes, a number of nodes being m in total, one of the points at the both ends is a ground node, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd-numbered nodes and lead the odd-numbered nodes to a first output port, the second electrical path being configured to combine even-numbered nodes and lead the even-numbered nodes to a second output port, the capacitors being provided correspond to at least (m −1) nodes excluding the ground node, and
a ground electrical path being configured to connect the ground node directly to the first output port without an interposed capacitor;

the rear stage circuit comprising:
an element series unit composed of a pair of semiconductor elements that are connected in series to each other and perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being connected to the first output port and to a grounded end of the load while the other end of the element series unit being connected to the second output port, and
inductors provided on a third electrical path and a fourth electrical path, respectively, the third electrical path being configured to lead a non-grounded end of the element series unit to the grounded end of the load, the fourth electrical path being configured to lead a mutual connection point of the pair of semiconductor elements to a non-grounded end of the load; and

a control section configured to control ON/OFF operations of the switches.

2. The transformer according to claim 1 , wherein
under a condition that a time period from a dead-time start time to a dead-time end time is a dead time (τ), the dead-time start time being a time at which control for the odd-numbered switches and control for the even-numbered switches are both turned OFF, the dead-time end time being a time at which control for either the odd-numbered switches or the even-numbered switches is turned ON,
the control section, after the dead-time start time, calculates a first half time (τ 1 ) and a second half time (τ 2 ), the first half time (τ 1 ) being calculated on the basis of electric charges that move from the inductor of the third electrical path to floating capacitances of the switches while one of the semiconductor elements is in a conductive state, the second half time (τ 2 ) being calculated on the basis of electric charges that move from the inductor of the third electrical path to the floating capacitances of the switches while the other semiconductor element is in a conductive state, and the control section determines the dead time (τ)on the basis of the first half time (τ 1 ) and the second half time (τ 2 ).

3. The transformer according to claim 2 , wherein the control section terminates the dead time (τ) before the electric charges that have moved to the floating capacitances return to the inductor of the third electrical path.

4. The transformer according to claim 3 , wherein
under a condition that a switching cycle of the switches is T, an inductance of the inductor of the third electrical path is L 1 , and a resistance value of the load is R 3 , the dead time (τ) satisfies the following relationship:
τ 1 +τ 2 ≤τ≤τ 0 +τ 1

where

τ
0

=

T
4

-

L
1

4
⁢

R
3

τ
1

=

T
4

+

L
1

4
⁢

R
3

-

1
4

⁢

(

T
+

L
1

R
3

)

2

-

32
⁢

L
1

⁢

∑

n
=
1

n

⁢

C
nDS

τ
2

=

T
4

-

L
1

4
⁢

R
3

-

1
4

⁢

(

T
-

Assignees

• Sumitomo Electric Industries
• National Univ Corporation Toyohashi Univ Of Technology

Inventors

• Nakahata Hideaki
• Hatsukawa Satoshi
• Hirotsu Kenichi
• Ohira Takashi
• Yamada Kyohei
• Egashira Daiya

Classifications

• H02M5/22

  using discharge tubes with control electrode or semiconductor devices with control electrode · CPC title

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M5/293

  using semiconductor devices only · CPC title

• H02M3/155 Primary

  using semiconductor devices only · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title