Variable capacitor based on buried oxide process

Patent metadata

Field	Value
Publication number	US-10115835-B2
Application number	US-201615250493-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Aug 29, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

Certain aspects of the present disclosure provide a semiconductor variable capacitor based on a buried oxide process. The semiconductor variable capacitor generally includes a first conductive pad coupled to a first non-insulative region and a second conductive pad coupled to a second non-insulative region. The second non-insulative region may be coupled to a semiconductor region. The capacitor may also include a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region. The capacitor also includes an insulator region disposed below the semiconductor region, wherein at least a portion of the first non-insulative region is separated from the second non-insulative region by the insulator region such that the first conductive pad is electrically isolated from the second conductive pad.

First claim

What is claimed is:

1. A semiconductor variable capacitor comprising:
a substrate;
a first conductive pad coupled to a first non-insulative region;
a second conductive pad coupled to a second non-insulative region, wherein the second non-insulative region is coupled to a first semiconductor region;
a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region; and
a first insulator region between the first semiconductor region and the substrate with respect to an axis perpendicular to the substrate, wherein at least a portion of the first non-insulative region is separated from the first semiconductor region by the first insulator region such that the first conductive pad is electrically isolated from the second conductive pad.

2. The capacitor of claim 1 , wherein the capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying the control voltage applied to the first control region with respect to the second conductive pad.

3. The capacitor of claim 1 , wherein the at least the portion of the first non-insulative region comprises a second semiconductor region, wherein the first insulator region is between the first semiconductor region and the second semiconductor region, wherein the second semiconductor region and the second non-insulative region are electrically isolated by the first insulator region.

4. The capacitor of claim 1 , further comprising:
a third conductive pad coupled to a third non-insulative region; and
a second control region coupled to a second semiconductor region such that a capacitance between the second conductive pad and the third conductive pad is configured to be adjusted by varying a control voltage applied to the second control region.

5. The capacitor of claim 4 , wherein the third non-insulative region is coupled to the second semiconductor region.

6. The capacitor of claim 4 , further comprising:
a second insulator region disposed below the second semiconductor region, wherein at least a portion of the third non-insulative region is electrically isolated from the second non-insulative region by the second insulator region.

7. The capacitor of claim 6 , wherein the portion of the third non-insulative region comprises a third semiconductor region disposed below the second insulator region, wherein the third semiconductor region and the second non-insulative region are electrically isolated by the second insulator region.

8. The capacitor of claim 6 , wherein the first insulator region and the second insulator region are separate regions.

9. The capacitor of claim 4 , further comprising a fourth conductive pad coupled to a fourth non-insulative region, wherein the fourth non-insulative region is coupled to the second semiconductor region, wherein the second conductive pad is coupled to the fourth conductive pad.

10. The capacitor of claim 9 , wherein the fourth non-insulative region is a separate region than the second non-insulative region and separated via trench isolation.

11. The capacitor of claim 4 , wherein the second control region is coupled to the first control region.

12. The capacitor of claim 1 , wherein the first non-insulative region and the second non-insulative region are separated via trench isolation.

13. The capacitor of claim 1 , wherein the first non-insulative region and the first semiconductor region are disposed on opposite sides of the first insulator region.

14. The capacitor of claim 13 , further comprising a second control region coupled to a second insulator region, wherein the second insulator region is coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying another control voltage applied to the second control region.

15. The capacitor of claim 1 , wherein the second non-insulative region is coupled to the first semiconductor region by a via through the first insulator region.

16. The capacitor of claim 1 , wherein the first control region is coupled to the first semiconductor region by a via through the first insulator region.

17. The capacitor of claim 1 , wherein the first insulator region is between the first control region and the at least the portion of the first non-insulative region with respect to the axis perpendicular to the substrate.

18. A method for fabricating a semiconductor variable capacitor, comprising:
forming an insulator region;
forming a semiconductor region above the insulator region, wherein the insulator region is formed between the semiconductor region and a substrate with respect to an axis perpendicular to the substrate;
forming a first non-insulative region;
coupling a first conductive pad to the first non-insulative region;
forming a second non-insulative region coupled to the semiconductor region formed above the insulator region;
coupling a second conductive pad to the second non-insulative region, wherein at least a portion of the first non-insulative region is separated from the semiconductor region by the insulator region such that the first conductive pad is electrically isolated from the second conductive pad; and
forming a control region coupled to the semiconductor region such that a control voltage applied to the control region is configured to adjust a capacitance between the first conductive pad and the second conductive pad.

Assignees

• Qualcomm Inc

Inventors

• Carobolante Francesco
• Marino Fabio Alessio

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H01L29/93 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/66189

  Electricity · mapped topic

• H01L27/0808

  Electricity · mapped topic