Thin film transistor array substrate and manufacture method of thin film transistor array substrate

Patent metadata

Field	Value
Publication number	US-10115748-B2
Application number	US-201615033624-A
Country	US
Kind code	B2
Filing date	Feb 18, 2016
Priority date	Jan 22, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

Provided are a thin film transistor array substrate and a manufacture method thereof, comprising: providing a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located; forming a gate on the first surface; forming a first insulative layer, which covers on the gate; forming a metal oxide semiconductor layer on the first insulative layer; implementing ion implantation to two end regions of the metal oxide semiconductor layer, and the two end regions after the ion implantation respectively are a source and a drain, and a region without the ion implantation is an active layer; forming a second insulative layer, which covers the source, the drain and the active layer; opening a via exposing the source or the drain in the second insulative layer; forming a pixel electrode on the second insulative layer, and connected with the source or the drain through the via.

First claim

What is claimed is:

1. A manufacture method of a thin film transistor array substrate, wherein the manufacture method of the thin film transistor array substrate comprises:
providing a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located;
forming a gate, and the gate is located on the first surface;
forming a first insulative layer, and the first insulative layer covers on the gate;
forming a metal oxide semiconductor layer on the first insulative layer;
implementing ion implantation to two end regions of the metal oxide semiconductor layer, and the two end regions of the metal oxide semiconductor layer after the ion implantation respectively are a source and a drain, and a region of the metal oxide semiconductor layer without the ion implantation is an active layer;
forming a second insulative layer, and the second insulative layer covers the source, the drain and the active layer;
opening a via employed to expose the source or the drain in the second insulative layer;
forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and is connected with the source or the drain through the via;
wherein the step of opening a via employed to expose the source or the drain in the second insulative layer comprises:
opening a first via and a second via in the second insulative layer, and the first via is located corresponding to the source, and the second via is located corresponding to the drain;
correspondingly, the step of forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and is connected with the source or the drain through the via comprises:
forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and the pixel electrode is connected with the drain through the second via;
the manufacture method of the thin film transistor array substrate further comprises:
forming a first electrode, and the first electrode is connected with the source through the first via;
wherein the step of opening a first via and a second via in the second insulative layer, and the first via is located corresponding to the source, and the second via is located corresponding to the drain comprises:
covering the second insulative layer with a second photoresist layer;
patterning the second photoresist layer to remove the second photoresist layer correspondingly right above the source and the drain to expose a portion of the second photoresist layer;
employing the patterned second photoresist layer as a mask to etch the second photoresist layer to open the first via and the second via in the second insulative layer;
stripping the second photoresist layer; and
wherein the pixel electrode and the first electrode are manufactured in the same process:
forming a transparent conductive layer, and the transparent conductive layer covers the second insulative layer, the source and the drain;
patterning the transparent conductive layer to preserve the transparent conductive layer located on the source and the drain, and a transparent conductive layer connected with the transparent conductive layer located on the drain, wherein the transparent conductive layer located on the source is the first electrode, and the transparent conductive layer located on the drain is the pixel electrode.

2. The manufacture method of the thin film transistor array substrate according to claim 1 , wherein the step of implementing ion implantation to two end regions of the metal oxide semiconductor layer, and the two end regions of the metal oxide semiconductor layer after the ion implantation respectively are a source and a drain, and a region of the metal oxide semiconductor layer without the ion implantation is an active layer comprises:
covering the metal oxide semiconductor layer with a first photoresist layer;
patterning the first photoresist layer to expose the two end regions of the metal oxide semiconductor layer;
employing the patterned first photoresist layer as a mask to implement the ion implantation to the metal oxide semiconductor layer, and the two end regions of the metal oxide semiconductor layer after the ion implantation respectively are the source and the drain, and the region of the metal oxide semiconductor layer without the ion implantation is the active layer;
stripping the first photoresist layer.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelectronics Co Ltd

Inventors

• Yao Jiangbo

Classifications

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H01L29/22

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic