Semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10115705-B2
Application number	US-201615211534-A
Country	US
Kind code	B2
Filing date	Jul 15, 2016
Priority date	Aug 8, 2012
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor device electrically connected to a second semiconductor device, wherein:
the first semiconductor device comprises a first surface, and the first surface comprises at least a first portion and a second portion that does not overlap with the first portion, wherein the first portion is a portion of the first surface that is not under the second semiconductor device; a first encapsulant material surrounding side edges of the first semiconductor device; a first dielectric layer above the first encapsulant material and the first portion; at least one redistribution layer (RDL) above the first dielectric layer; a second dielectric layer above the at least one RDL and the second portion, wherein:
a maximum thickness of the second dielectric layer above the second portion and adjacent to the second semiconductor device is less than a sum of the thicknesses of the first dielectric layer above the first portion, the at least one RDL, and the second dielectric layer above the at least one RDL; and
a passivation layer directly above the first surface, wherein:
the passivation layer directly contacts both the first dielectric layer and the first surface, and
the passivation layer directly contacts both the second dielectric layer and the first surface.

2. The package according to claim 1 , wherein at least one of the first dielectric layer, the second dielectric layer, and the passivation layer comprises at least one of polymide, epoxy, benzocyclobutene (BCB), and polybenzoxazole (PBO).

3. The package according to claim 1 , wherein the first surface of the first semiconductor device is coplanar with the first surface of the first encapsulant material.

4. The package according to claim 1 , wherein a second surface of the first semiconductor device opposite to the first surface is coupled to a circuit board.

5. The package according to claim 4 , wherein the first semiconductor device, the at least one RDL, the second semiconductor device, and a top surface of the circuit board are covered with a second encapsulant material.

6. The package according to claim 5 , wherein the first and second encapsulant materials comprise an epoxy-series resin.

7. A semiconductor package comprising:
a first semiconductor device electrically connected to a second semiconductor device, wherein:
the first semiconductor device comprises a first surface, and the first surface comprises at least a first portion and a second portion; a first encapsulant material surrounding side edges of the first semiconductor device; a first dielectric layer above the first encapsulant material and the first portion; at least one redistribution layer (RDL) above the first dielectric layer; a second dielectric layer above the at least one RDL and the second portion, wherein a second lower surface of the second dielectric layer above the first portion is higher than a first an upper surface of the second dielectric layer above the second portion; and
a passivation layer directly above the first surface, wherein:
the passivation layer contacts both the first dielectric layer and the first surface, and
the passivation layer contacts both the second dielectric layer and the first surface.

8. The package according to claim 7 , wherein at least one of the first dielectric layer, the second dielectric layer, and the passivation layer comprises at least one of polymide, epoxy, benzocyclobutene (BCB), and polybenzoxazole (PBO).

9. The package according to claim 7 , wherein the first surface of the first semiconductor device is coplanar with the first surface of the first encapsulant material.

10. The package according to claim 7 , wherein a second surface of the first semiconductor device opposite to the first surface is coupled to a circuit board.

11. The package according to claim 10 , wherein the first semiconductor device, the at least one RDL, the second semiconductor device, and a top surface of the circuit board are covered with a second encapsulant material.

12. The package according to claim 11 , wherein the first and second encapsulant materials comprise an epoxy-series resin.

13. A semiconductor package comprising:
a first semiconductor device electrically connected to a second semiconductor device, wherein:
the first semiconductor device comprises a first surface, and the first surface comprises at least a perimeter portion and an inner portion; a first encapsulant material surrounding side edges of the first semiconductor device; a first dielectric layer above the first encapsulant material and the perimeter portion; at least one redistribution layer (RDL) above the first dielectric layer; a second dielectric layer above the at least one RDL and the inner portion; and a passivation layer directly above the first surface, wherein:
the second dielectric layer is over the first encapsulant material, the perimeter portion, and the inner portion,
the first dielectric layer is only over the first encapsulant material and the perimeter portion,
the passivation layer directly contacts both the first dielectric layer and the first surface, and
the passivation layer directly contacts both the second dielectric layer and the first surface.

14. The package according to claim 13 , wherein at least one of the first dielectric layer, the second dielectric layer, and the passivation layer comprises at least one of polymide, epoxy, benzocyclobutene (BCB), and polybenzoxazole (PBO).

15. The package according to claim 13 , wherein the first surface of the first semiconductor device is coplanar with the first surface of the first encapsulant material.

16. The package according to claim 13 , wherein a second surface of the first semiconductor device opposite to the first surface is coupled to a circuit board.

17. The package according to claim 16 , wherein the first semiconductor device, the at least one RDL, the second semiconductor device, and a top surface of the circuit board are covered with a second encapsulant material.

18. The package according to claim 17 , wherein the first and second encapsulant materials comprise an epoxy-series resin.

Assignees

• Amkor Technology Inc

Inventors

• Kim Jin Young
• Park No Sun
• Kim Yoon Joo
• Lee Choon Heung
• Kim Jin Han
• Lee Seung Jae
• Cha Se Woong
• Kim Sung Kyu
• Rinne Glenn

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title