Buried thermally conductive layers for heat extraction and shielding

Patent metadata

Field	Value
Publication number	US-10115654-B2
Application number	US-81902210-A
Country	US
Kind code	B2
Filing date	Jun 18, 2010
Priority date	Jun 18, 2010
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

An embodiment is a method and apparatus for heat extraction and shielding in multi-block semiconductor devices. A plurality of blocks stacked on each other is interconnected by vertical vias filled with thermally conducting material and separated by buried thermally conductive layers. A thermally conductive layer is bonded to bottom or top of the plurality of blocks as a ground plane or a heat extraction layer. The thermally conductive layer has a high thermal conductivity.
An embodiment is a method and apparatus for heat extraction and shielding in single-block semiconductor devices. A thermally insulative layer is deposited on a substrate. The thermally insulative layer is capable of supporting a thermal gradient to reduce heating of the substrate. A buried thermally conductive layer is formed inside the thermally insulative layer and has a vertical via to connect through the substrate to an external heat extracting layer. A semiconductor layer is deposited on the thermally insulative layer and patterned for electrical interconnects.

First claim

What is claimed is:

1. A device comprising:
a plurality of blocks grown sequentially on each other, the plurality of the blocks being interconnected by vertical vias filled with thermally conducting material, wherein each of the blocks comprises:
an insulating layer,
a semiconductor layer being deposited on the insulating layer below,
a thermally insulating layer being deposited on the semiconductor layer below, and
a buried thermally conductive layer being deposited on the thermally insulating layer below; and

a thermally conductive layer bonded to bottom or top of the plurality of blocks as a ground plane or a heat extraction layer, the thermally conductive layer having a high thermal conductivity,
wherein
the vertical vias contact the thermally conductive layer and pass through the insulating layer, the thermally insulating layer, and the buried thermally conductive layer in the plurality of blocks,
the vertical vias do not contact the semiconductor layers of the plurality of blocks, and
inter-plane vias connect the semiconductor layers of the plurality of blocks.

2. The device of claim 1 wherein
the insulating layer is an amorphous thermally insulating substrate, wherein the semiconductor layer is patterned for electrical interconnects, and
wherein the amorphous thermally insulating substrate is different in composition from the thermally insulating layer.

3. The device of claim 1 further comprising:
at least one vertical metal interconnect to interconnect the buried thermally conductive layer and the thermally conductive layer.

4. The device of claim 1 , wherein
the vertical vias interconnect the plurality of blocks and the thermally conductive layer.

5. The device of claim 1 wherein the thermally conductive layer has a thermal conductivity higher than 200 W/m/K.

6. A method comprising:
forming a plurality of blocks grown sequentially on each other, the plurality of the blocks being interconnected by vertical vias filled with thermally conducting metal, wherein forming a plurality of the blocks comprises forming each of the blocks, wherein forming each of the blocks comprises:
depositing the semiconductor layer on an insulating layer below, and
depositing a thermally insulating layer on the semiconductor layer below, and
depositing a buried thermally conductive layer on the thermally insulating layer below; and

forming a thermally conductive layer at the bottom or at the top of the plurality of blocks as a ground plane or a heat extraction layer, the thermally conductive layer having a high thermal conductivity,
wherein
the vertical vias contact the thermally conductive layer and pass through the insulating layer, the thermally insulating layer, and the buried thermally conductive layer in the plurality of blocks,
the vertical vias do not contact the semiconductor layers of the plurality of blocks, and
inter-plane vias connect the semiconductor layers of the plurality of blocks.

7. The method of claim 6 wherein forming each of the blocks comprises:
creating an amorphous thermally insulating substrate, the amorphous thermally insulating substrate being the insulating layer,
wherein the semiconductor layer is patterned for electrical interconnects, and
wherein the amorphous thermally insulating substrate is different in composition from the thermally insulating layer.

8. The method of claim 6 further comprising:
forming a vertical metal interconnect to interconnect the buried thermally conductive layers and the thermally conductive layer.

9. The method of claim 6 further comprising:
forming the vertical vias to interconnect the buried thermally conductive layers and the thermally conductive layer.

10. The method of claim 6 wherein the thermally conductive layer has a thermal conductivity higher than 200 W/m/K.

Assignees

• Biegelsen David K
• Apte Raj B
• Palo Alto Res Ct Inc

Inventors

• Biegelsen David K
• Apte Raj B

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W40/228 Primary

  the projecting parts being wire-shaped or pin-shaped · CPC title

• H10W40/00 Primary

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• H01L2924/12044

  Electricity · mapped topic