Semiconductor arrangement, semiconductor system and method of forming a semiconductor arrangement

Patent metadata

Field	Value
Publication number	US-10115646-B2
Application number	US-201615149207-A
Country	US
Kind code	B2
Filing date	May 9, 2016
Priority date	Jun 10, 2015
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power semiconductor devices arranged on the surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices may be electrically coupled to the electrically conductive plate, a plurality of electrically conductive blocks, wherein each electrically conductive block may be electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the surface of the electrically conductive plate may be free from the encapsulation material.

First claim

What is claimed is:

1. A semiconductor arrangement, comprising:
an electrically conductive plate having a top surface;
a plurality of power semiconductor devices arranged on the top surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices is electrically coupled to the electrically conductive plate;
a plurality of electrically conductive blocks, each electrically conductive block being electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and
encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the top surface of the electrically conductive plate is free from the encapsulation material.

2. The semiconductor arrangement of claim 1 ,
wherein at least one portion of a top surface of the semiconductor arrangement opposite the electrically conductive plate is electrically coupled with the respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices.

3. The semiconductor arrangement of claim 2 ,
wherein the semiconductor arrangement is configured to have a current flowing between the at least one portion of the top surface and the electrically conductive plate.

4. The semiconductor arrangement of claim 1 , further comprising at least one control terminal for controlling a current between the first controlled terminal and the second controlled terminal of at least one power semiconductor device of the plurality of power semiconductor devices.

5. The semiconductor arrangement of claim 1 , further comprising a sealing structure.

6. The semiconductor arrangement of claim 5 , wherein the sealing structure comprises a sealing element.

7. The semiconductor arrangement of claim 6 , wherein the sealing element is a sealing ring.

8. The semiconductor arrangement of claim 6 , wherein the sealing element is arranged on the at least one edge region of the top surface of the electrically conductive plate.

9. The semiconductor arrangement of claim 6 , wherein the sealing element is embedded in the encapsulation material.

10. The semiconductor arrangement of claim 1 , wherein the encapsulation material comprises sealing properties.

11. The semiconductor arrangement of claim 1 , further comprising an electrically conductive layer arranged over the plurality of electrically conductive blocks and over the encapsulation material.

12. The semiconductor arrangement of claim 11 , wherein the electrically conductive layer, a sealing structure and the electrically conductive plate are arranged to form at least part of an hermetic sealing of the plurality of semiconductor devices.

13. The semiconductor arrangement of claim 1 , wherein the plurality of power semiconductor devices comprises a plurality of IGBTs.

14. The semiconductor arrangement of claim 1 , wherein the plurality of power semiconductor devices comprises at least one power diode.

15. The semiconductor arrangement of claim 1 ,
wherein the electrically conductive plate further comprises a second surface opposite the top surface and a side surface connecting the top surface and the second surface; and
wherein the second surface and the side surface are free from the encapsulation material.

16. The semiconductor arrangement of claim 1 ,
wherein the electrically conductive plate and/or the plurality of electrically conductive blocks comprises at least one electrically conductive material of the group of electrically conductive materials consisting of
molybdenum;
copper; and
carbon.

17. The semiconductor arrangement of claim 2 ,
wherein a connecting surface between the at least one portion of the top surface of the semiconductor arrangement and the electrically conductive plate comprises a structure increasing a distance along a surface of the structure between the at least one portion of the top surface of the semiconductor arrangement and the electrically conductive plate.

18. A semiconductor system comprising a plurality of semiconductor arrangements, each semiconductor arrangement comprising:
an electrically conductive plate having a top surface;
a plurality of power semiconductor devices arranged on the top surface of the electrically conductive plate, wherein a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices is electrically coupled to the electrically conductive plate;
a plurality of electrically conductive blocks, each electrically conductive block being electrically coupled with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and
encapsulation material encapsulating the plurality of power semiconductor devices, wherein at least one edge region of the top surface of the electrically conductive plate is free from the encapsulation material.

19. A method of forming a semiconductor arrangement, the method comprising:
arranging a plurality of power semiconductor devices on a top surface of an electrically conductive plate;
electrically coupling a first controlled terminal of each power semiconductor device of the plurality of power semiconductor devices to the electrically conductive plate;
electrically coupling each electrically conductive block of a plurality of electrically conductive blocks with a respective second controlled terminal of each power semiconductor device of the plurality of power semiconductor devices; and
encapsulating the plurality of power semiconductor devices with encapsulation material such that at least one edge region of the top surface of the electrically conductive plate is free from the encapsulation material.

20. The method of claim 19 , wherein the encapsulating comprises molding.

21. The method of claim 20 , wherein the molding comprises one of transfer molding and compression molding.

22. The method of claim 21 , wherein, during the transfer molding, a surface of each of the plurality of electrically conductive blocks facing away from the respective power semiconductor device of the plurality of power semiconductor devices remains free from the encapsulation material.

23. The method of claim 19 , further comprising:
arranging a sealing element on the at least one edge region.

24. The method of claim 23 , wherein the sealing element is a sealing ring.

25. The method of claim 19 , further comprising:
arranging an electrically conductive layer over the plurality of electrically conductive blocks and over the encapsulation material.

26. The method of claim 24 , further comprising:
forming an hermetic sealing for the plurality of power semiconductor devices by forming an hermetically sealed connection between the electrically conductive layer and the sealing ring and by pressing the sealing ring onto the at least one edge region.

Assignees

• Infineon Technologies Ag

Inventors

• Hoegerl Juergen
• Fuergut Edward

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10 Primary

  characterised by their shape or disposition · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title