Method for fabricating auto-aligned interconnection elements for a 3D integrated circuit

Patent metadata

Field	Value
Publication number	US-10115637-B2
Application number	US-201715820811-A
Country	US
Kind code	B2
Filing date	Nov 22, 2017
Priority date	Nov 23, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

Method for fabricating transistors for an integrated 3D circuit, comprising:
a) forming, on a given level of transistors made in a first semiconductor layer: a stack comprising a first region of a second semiconductor zone suitable for an N-type transistor channel and a second region of the second semiconductor zone suitable for a P-type transistor channel of a higher level, the stack moreover comprising a ground plane continuous layer ( 40 ), as well as an insulating layer between the ground plane and the second semiconductor layer, then b) exposing source and drain zones of the circuit to a laser (L), so as to carry out at least one thermal activation annealing, where the exposed source and drain zones are located next to an upper surface of the ground plane continuous layer, where the ground plane continuous layer is configured so as to protect at least a part of the circuit located on the side of a lower face of the ground plane continuous layer from the laser, then c) carrying out cutting up of the ground plane continuous layer ( 40 ) into at least one first portion and one second portion separated from the first portion, where the first portion is configured to allow biasing of the first region, where the second portion is configured to allow biasing of the second region.

First claim

The invention claimed is:

1. Method for fabricating transistors for an integrated circuit equipped with several superimposed levels of transistors, comprising the following steps:
a) forming, on a given level equipped with one or more transistors made at least partially in a first semiconductor layer: a stack comprising at least one first region of a second semiconductor layer suitable for receiving an N-type transistor channel and at least one second region of the second semiconductor zone suitable for receiving a P-type transistor channel of a level above the given level, where the stack moreover comprises a continuous layer made of conductive or doped semiconductor material and called the ground plane, as well as an insulating layer between the ground plane and the second semiconductor layer, then
b) carrying out at least one thermal annealing for activation of source and drain region of said N type transistor and of said P type transistor by exposure to a laser, said source and drain regions being in the form of one or more doped zones of the second semiconductor layer and/or doped semiconductor blocks formed on the second semiconductor layer, where the source and drain regions exposed to the laser are located on the side of an upper face of the ground plane continuous layer, where the ground plane continuous layer is configured so as to protect from the laser a part of the circuit located on the side of a lower face of the ground plane continuous layer, then
c) cutting up of the ground plane continuous layer into at least one first portion and at least one second portion separated from the first portion, where the first portion is configured to allow biasing of the first region, where the second portion is configured to allow biasing of the second region.

2. The method according to claim 1 , wherein the ground plane continuous layer is based on doped semiconductor material, where the first portion is P doped, with the second portion being N doped.

3. The method according to claim 1 , wherein the formation of the stack comprises the etching of the second semiconductor layer so as to form islands suitable for creating active zones of transistors, where the ground plane is kept continuous at the end of the etching.

4. The method according to claim 1 , comprising, after formation of islands and prior to the activation of the source and drain regions of said transistor, the formation of a first sacrificial gate and of a second sacrificial gate, where the method moreover comprises, after performing the cutting up of the ground plane layer, steps for:
removal of sacrificial gates and their respective replacement with a first replacement gate and a second replacement gate.

5. The method according to claim 1 , comprising, prior to the cutting up of the ground plane continuous layer, the formation of a first sacrificial gate and a second sacrificial gate and a sacrificial linking element between the first sacrificial gate and the second sacrificial gate, then:
performing the cutting up of the ground plane continuous layer by forming a trench between the first sacrificial gate and the second sacrificial gate, where the trench passes through the sacrificial linking element and the ground plane continuous layer so as to separate the first portion and the second portion,
filling the trench using at least one insulating material,
removal of the sacrificial gates and replacing them with, respectively, a first replacement gate, a second replacement gate, and a connection element linking the first replacement gate and the second replacement gate.

6. The method according to claim 5 wherein filling the trench comprises steps for:
the deposition of a layer of a first insulating material which lines the trench and covers the first sacrificial gate and the second sacrificial gate, then of a layer of a second insulating material on the first insulating material, so as to obtain said filling,
the method moreover comprising prior to the removal of the sacrificial gates:
planarization of the layer of second insulating material so as to remove the second insulating material facing the first sacrificial gate and the second sacrificial gate,
formation of holes in the layer of the first insulation material, where the holes reveal the first sacrificial gate and the second sacrificial gate.

7. The method according to claim 5 wherein the trench comprises a principal region of width Δ 2 greater than the width L of the sacrificial gates and a narrowed region of width Δ 1 <Δ 2 of the sacrificial gates, where the narrowed region separates the first sacrificial gate and the second sacrificial gate.

8. The method according to claim 1 , wherein the formation of the stack comprises the etching of the second semiconductor layer so as to form islands suitable for forming active zones of transistors, the method comprising, prior to cutting up of the ground plane continuous layer:
formation of a first sacrificial gate and a second sacrificial gate and a sacrificial linking element, where the islands and sacrificial gates are surrounded by a first encapsulation layer,
removal of the sacrificial gates and their replacement with, respectively, a first replacement gate, a second replacement gate, and a connection element linking the first replacement gate and the second replacement gate, then
removal of the first encapsulation layer and replacement with a second encapsulation layer based on silsesquioxane derivative RSiO 3/2 , where the second encapsulation layer extends around the islands and beneath the connection element linking a gate of a P type transistor and a gate of an N type transistor,
exposing a block of the second encapsulation layer which extends between the connection element and the ground plane layer using a laser or electron beam,
removing this block so as to form a trench between the first replacement gate and the second replacement gate, where the trench passes through the connection element and the ground plane continuous layer,
the cutting up of the ground plane continuous layer into a first portion and at least one second portion separated from the first portion, being carried out by etching in the extension of the trench.

9. The method according to claim 1 , wherein the exposure is performed using a UV laser with short pulses between 40 ns and 160 ns.

Assignees

• Commissariat Energie Atomique

Inventors

• Fenouillet-Beranger Claire
• Mathieu Benoit
• Coronel Philippe

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title