Method of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-10115602-B2
Application number	US-201715444597-A
Country	US
Kind code	B2
Filing date	Feb 28, 2017
Priority date	Jul 27, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A method of manufacturing a semiconductor device includes alternately stacking mold insulating layers and sacrificial layers on a substrate; forming channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing recessed regions to be formed in the substrate; cleaning a surface of the recessed regions in such a manner that processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ; and forming epitaxial layers on the recessed regions of the substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
alternately stacking mold insulating layers and sacrificial layers on a substrate;
forming a plurality of channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing a plurality of recessed regions to be formed in the substrate;
cleaning a surface of the plurality of recessed regions, wherein processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the plurality of recessed regions in a lower portion of the channel holes are alternately repeated one or more times, in-situ;
forming epitaxial layers on the plurality of recessed regions of the substrate using the substrate in the plurality of recessed regions as seed;
forming a gate dielectric layer and a first semiconductor layer, covering a side wall of each of the channel holes and a top surface of the epitaxial layers;
forming a spacer on the gate dielectric layer, wherein processes of forming a second protective layer in the upper region of the channel holes and performing the anisotropic dry etching process on the first semiconductor layer are alternately repeated one or more times, in-situ;
removing a portion of the gate dielectric layer on the top surface of the epitaxial layers, wherein processes of forming a third protective layer in the upper region of the channel holes and performing the anisotropic dry etching process on the gate dielectric layer using the spacer as an etching mask are alternately repeated one or more times, in-situ; and
forming second semiconductor layers connected to the epitaxial layer in the channel holes.

2. The method of claim 1 , wherein the forming of the spacer and the removing of a portion of the gate dielectric layer are performed in the same etching chamber in sequence.

3. The method of claim 1 , further comprising:
forming a mask layer on the mold insulating layers and the sacrificial layers,
wherein the channel holes penetrate through the mask layer.

4. The method of claim 3 , wherein in the forming of the spacer and the removing of a portion of the gate dielectric layer, the second protective layer and the third protective layer prevent the mask layer from being etched.

5. The method of claim 1 , further comprising:
forming insulating layers filling a remaining portion of a space of the channel holes; and
forming conductive pads connected to the second semiconductor layers on the insulating layers.

6. The method of claim 1 , wherein the gate dielectric layer comprises a charge trapping layer including a silicon nitride or a silicon oxynitride.

7. A method of manufacturing a semiconductor device, comprising:
alternately stacking mold insulating layers and sacrificial layers on a substrate;
forming channel holes penetrating through the mold insulating layers and the sacrificial layers and allowing recessed regions to be formed in the substrate;
cleaning a surface of the recessed regions in such a manner that processes of forming a first protective layer in an upper region of the channel holes and performing an anisotropic dry etching process on the recessed regions are alternately repeated one or more times, in-situ;
forming an epitaxial layer in the recessed regions of the substrate;
forming a gate dielectric layer and a first semiconductor layer, covering a side wall of the channel holes and a top surface of the epitaxial layer;
forming a spacer on the gate dielectric layer in such a manner that processes of forming a second protective layer in the upper region of the channel holes and performing the anisotropic dry etching process on the first semiconductor layer are alternately repeated one or more times, in-situ;
removing a portion of the gate dielectric layer on the top surface of the epitaxial layer in such a manner that processes of forming a third protective layer in the upper region of the channel holes and performing the anisotropic dry etching process on the gate dielectric layer using the spacer as an etching mask are alternately repeated one or more times, in-situ; and
forming second semiconductor layers connected to the epitaxial layer in the channel holes.

8. The method of claim 7 , wherein the first protective layer, the second protective layer, and the third protective layer are provided as a film containing C or Si.

9. The method of claim 7 , further comprising:
forming insulating layers filling a remaining portion of a spacer of the channel holes; and
forming conductive pads connected to the second semiconductor layers on the insulating layers.

Assignees

• Jung Seung Jae
• Yoon Sang Joon
• Kwon Yong Hyun
• Jang Dae Hyun
• Kim Ha Na
• Samsung Electronics Co Ltd

Inventors

• Jung Seung Jae
• Yoon Sang Joon
• Kwon Yong Hyun
• Jang Dae Hyun
• Kim Ha Na

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/244

  comprising alternated and repeated etching and passivation steps · CPC title