Multilayer ceramic capacitor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10115524-B2
Application number	US-201715586320-A
Country	US
Kind code	B2
Filing date	May 4, 2017
Priority date	May 11, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

In a width direction of a ceramic laminate, one end portion of a first internal electrode and one end portion of a second internal electrode each include metal phases of a Ni region, a Ni—O region, and a Ni—O—Mg region disposed in this order from a first internal electrode side and a second internal electrode side, respectively, to a first side surface of the ceramic laminate. The other end portion of the first internal electrode and the other end portion of the second internal electrode each include metal phases of a Ni region, a Ni—O region, and a Ni—O—Mg region disposed in this order from the first internal electrode side and the second internal electrode side, respectively, to a second side surface of the ceramic laminate.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a ceramic laminate in which a plurality of ceramic dielectric layers each including a surface on which a first internal electrode is provided, a plurality of ceramic dielectric layers each including a surface on which a second internal electrode is provided, and a plurality of ceramic dielectric layers provided with no internal electrodes, are laminated to each other, the ceramic laminate including a first main surface and a second main surface facing each other in a lamination direction, a first side surface and a second side surface facing each other in a width direction perpendicular or substantially perpendicular to the lamination direction, and a first end surface and a second end surface facing each other in a length direction perpendicular or substantially perpendicular to the lamination direction and the width direction;
in the width direction of the ceramic laminate, a first covering ceramic dielectric layer provided on the first side surface of the ceramic laminate to which one end portion of the first internal electrode and one end portion of the second internal electrode are exposed and a second covering ceramic dielectric layer provided on the second side surface of the ceramic laminate to which the other end portion of the first internal electrode and the other end portion of the second internal electrode are exposed; and
a first external electrode provided on the first end surface of the ceramic laminate to which the first internal electrode is exposed and a second external electrode provided on the second end surface of the ceramic laminate to which the second internal electrode is exposed; wherein
the first internal electrode and the second internal electrode face each other with the corresponding ceramic dielectric layer interposed therebetween;
in the width direction of the ceramic laminate, the one end portion of the first internal electrode includes metal phases of Ni, Ni—O, and Ni—Mg—O arranged in this order from a first internal electrode side to the first side surface of the ceramic laminate, and the other end portion of the first internal electrode includes metal phases of Ni, Ni—O, and Ni—Mg—O arranged in this order from the first internal electrode side to the second side surface of the ceramic laminate; and
in the width direction of the ceramic laminate, the one end portion of the second internal electrode includes metal phases of Ni, Ni—O, and Ni—Mg—O arranged in this order from a second internal electrode side to the first side surface of the ceramic laminate, and the other end portion of the second internal electrode includes metal phases of Ni, Ni—O, and Ni—Mg—O arranged in this order from the second internal electrode side to the second side surface of the ceramic laminate.

2. The multilayer ceramic capacitor according to claim 1 , wherein in the width direction of the ceramic laminate, the one end portion of the first internal electrode and the one end portion of the second internal electrode are each located within a displacement of approximately 5 μm or less along the lamination direction, and the other end portion of the first internal electrode and the other end portion of the second internal electrode are each located within a displacement of approximately 5 μm or less along the lamination direction.

3. The multilayer ceramic capacitor according to claim 1 , wherein corner portions of the ceramic laminate are rounded.

4. The multilayer ceramic capacitor according to claim 1 , wherein a size of the ceramic laminate is approximately 0.2 mm to approximately 0.8 mm in the lamination direction, approximately 0.2 mm to approximately 1.6 mm in the length direction, and approximately 0.2 mm to approximately 0.8 mm in the width direction.

5. The multilayer ceramic capacitor according to claim 1 , wherein in the length direction of the ceramic laminate, a gap is provided between a counter electrode portion of the first internal electrode and the second end surface.

6. The multilayer ceramic capacitor according to claim 1 , wherein in the length direction of the ceramic laminate, a gap is provided between a counter electrode portion of the second internal electrode and the first end surface.

7. The multilayer ceramic capacitor according to claim 1 , wherein the one end portion of the first internal electrode and the one end portion of the second internal electrode each extend from the first side surface of the ceramic laminate to a distance of approximately 10 μm toward an inside thereof.

8. The multilayer ceramic capacitor according to claim 1 , wherein the other end portion of the first internal electrode and the other end portion of the second internal electrode each extend from the second side surface of the ceramic laminate to a distance of approximately 10 μm toward an inside thereof.

9. The multilayer ceramic capacitor according to claim 1 , wherein lengths of regions include the Ni—Mg—O are each approximately 0.5 μm to approximately 1 μm.

10. The multilayer ceramic capacitor according to claim 1 , wherein the first internal electrode and the second internal electrode each include dielectric particles.

11. The multilayer ceramic capacitor according to claim 1 , wherein a thickness of each of the first internal electrode and the second internal electrode is approximately 0.3 μm to approximately 2.0 μm.

12. The multilayer ceramic capacitor according to claim 1 , wherein the ceramic laminate includes a total number of the first internal electrode and the second internal electrode of approximately 50 to approximately 850.

13. The multilayer ceramic capacitor according to claim 1 , wherein a thickness of each of the first covering ceramic dielectric layer and the second covering ceramic dielectric layer is approximately 5 μm to approximately 40 μm.

14. The multilayer ceramic capacitor according to claim 1 , wherein each of the first external electrode and the second external electrode layer includes an underlayer electrode layer and a plating layer.

15. The multilayer ceramic capacitor according to claim 14 , wherein the underlayer electrode layer includes at least one of a fired layer, a resin layer, and a thin-film layer.

16. The multilayer ceramic capacitor according to claim 14 , wherein the plating layer includes a plurality of layers.

17. The multilayer ceramic capacitor according to claim 14 , wherein the plating layer includes a Ni plating layer and a Sn plating layer.

18. The multilayer ceramic capacitor according to claim 1 , wherein
the first internal electrode and the second internal electrode each include Ni; and
the first covering ceramic dielectric layer and the second covering ceramic dielectric layer each include Mg.

Assignees

• Murata Manufacturing Co

Inventors

• Sugita Hiroaki

Classifications

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G4/1209

  characterised by the ceramic dielectric material (H01G4/1272, H01G4/1281 take precedence) · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/10

  Metal-oxide dielectrics {(H01G4/085 takes precedence)} · CPC title