Multi-layer stack with embedded tamper-detect protection

Patent metadata

Field	Value
Publication number	US-10115275-B2
Application number	US-201715791642-A
Country	US
Kind code	B2
Filing date	Oct 24, 2017
Priority date	Feb 25, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

First claim

What is claimed is:

1. A tamper-respondent assembly comprising:
a multi-layer stack comprising multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers;
a tamper-respondent electronic circuit structure embedded within the multi-layer stack, the tamper-respondent electronic circuit structure comprising at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack, the tamper-respondent electronic circuit structure defining a secure volume within the multi-layer stack; and
wherein the at least one tamper-respondent sensor comprises at least one peripheral tamper-detect circuit extending through a component layer of the at least one component layer of the multi-layer stack, the at least one peripheral tamper-detect circuit comprising a plurality of through-substrate vias disposed about the periphery of, and extending through, the component layer.

2. The tamper-respondent assembly of claim 1 , wherein the at least one tamper-respondent sensor embedded, at least in part, within the at least one component layer comprises multiple stacked tamper-detect circuits within one component layer of the at least one component layer of the multi-layer stack.

3. The tamper-respondent assembly of claim 1 , wherein the tamper-respondent electronic circuit structure is embedded within the multi-layer stack, and the secure volume resides fully within the multi-layer stack.

4. A tamper-respondent assembly comprising:
a multi-layer stack comprising multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers; and
a tamper-respondent electronic circuit structure within the multi-layer stack, the tamper-respondent electronic circuit structure comprising:
at least one tamper-respondent sensor, each tamper-respondent sensor being embedded, at least in part, within one or more component layers of the multiple discrete component layers of the multi-layer stack; and
monitor circuitry electrically connected to monitor the at least one tamper-respondent sensor for a tamper event, wherein the at least one tamper-respondent sensor and the monitor circuitry reside within, and facilitate defining a secure volume within, the multi-layer stack.

5. The tamper-respondent assembly of claim 4 , wherein the tamper-respondent electronic circuit structure defines the secure volume within at least two component layers of the multi-layer stack.

6. The tamper-respondent assembly of claim 4 , wherein the multi-layer stack comprises a first component layer, at least one in-between component layer, and a second component layer stacked together, the at least one in-between component layer being disposed between the first component layer and the second component layer in the multi-layer stack, and wherein the tamper-respondent electronic circuit structure is associated with the first component layer, the at least one in-between component layer, and the second component layer, with the secure volume being defined, at least in part, within the at least one in-between component layer.

7. A method of fabricating a tamper-respondent assembly comprising:
providing a multi-layer stack comprising multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers;
embedding a tamper-respondent electronic circuit structure within the multi-layer stack, the tamper-respondent electronic circuit structure comprising at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack, the tamper-respondent electronic circuit structure defining a secure volume within the multi-layer stack; and
wherein the at least one tamper-respondent sensor comprises at least one peripheral tamper-detect circuit extending through a component layer of the at least one component layer of the multi-layer stack, the at least one peripheral tamper-detect circuit comprising a plurality of through-substrate vias disposed about the periphery of, and extending through, the component layer.

8. The method of claim 7 , wherein the at least one tamper-respondent sensor embedded, at least in part, within the at least one component layer comprises multiple stacked tamper-detect circuits within one component layer of the at least one component layer of the multi-layer stack.

9. The method of claim 7 , wherein the tamper-respondent electronic circuit structure is embedded within the multi-layer stack, and the secure volume resides fully within the multi-layer stack.

Assignees

• IBM

Inventors

• Busby James A
• Isaacs Phillip Duane
• Santiago-Fernandez William

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W42/405

  using active circuits · CPC title