Distributed reservation based coherency protocol

Patent metadata

Field	Value
Publication number	US-10114748-B2
Application number	US-201615280383-A
Country	US
Kind code	B2
Filing date	Sep 29, 2016
Priority date	Sep 29, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A method of operating a cache-coherent computing system includes storing first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of a first plurality of processors. The method includes transmitting an output atomic response transaction indicating a status of the first reservation to a coherency interconnection in response to issuance of the first exclusive access to the coherency interconnection. The output atomic response transaction is based on first state information.

First claim

What is claimed is:

1. A method of operating a cache-coherent computing system comprising:
storing first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of a first plurality of processors, the first state information including a proxy monitor indicator and an exclusive-write-ready indicator;
maintaining a set state of the proxy monitor indicator and a reset state of the exclusive-write-ready indicator until receiving an atomic response transaction associated with a successful colliding access of the first memory address or until detecting selection for issuance of the first exclusive access; and
transmitting an output atomic response transaction indicating a status of the first reservation to a coherency interconnection in response to issuance of the first exclusive access to the coherency interconnection,
wherein the output atomic response transaction is based on the first state information.

2. The method, as recited in claim 1 , further comprising:
selectively forwarding to the first plurality of processors, a colliding exclusive access of the first memory address associated with a second reservation,
wherein the second reservation corresponds to a second exclusive access to the first memory address,
wherein the colliding exclusive access is selectively forwarded to the first plurality of processors according to status information included in at least one input atomic response transaction associated with a memory requestor other than the first plurality of processors.

3. The method, as recited in claim 1 , further comprising:
receiving an input atomic response transaction for each corresponding reservation to the first memory address, the input atomic response transaction including state information for the corresponding reservation; and
updating the status of the first reservation based on the state information in the input atomic response transaction.

4. The method, as recited in claim 1 , further comprising:
updating the first state information based on a status of a second reservation of a second exclusive access to the first memory address,
wherein the second exclusive access is associated with another thread executing on a second processor of a second plurality of processors.

5. The method, as recited in claim 1 , further comprising:
setting the proxy monitor indicator in response to the first exclusive access being a coherent access transaction and issuance of the first exclusive access by the first processor to the coherency interconnection.

6. The method, as recited in claim 5 , further comprising:
resetting the proxy monitor indicator in response to an indication of a successful exclusive access to the first memory address.

7. The method, as recited in claim 1 , further comprising:
setting the exclusive-write-ready indicator in response to receiving an indication of performance of the first exclusive access from the coherency interconnection.

8. The method, as recited in claim 1 , further comprising:
selectively forwarding a colliding snoop of the first memory address to the first plurality of processors according to the exclusive-write-ready indicator.

9. The method, as recited in claim 1 , further comprising:
resetting the exclusive-write-ready indicator in response to receiving an indication of completion of the first exclusive access.

10. The method, as recited in claim 1 , wherein the maintaining prevents a first subsequent exclusive access to the first memory address from invalidating a second reservation for a second subsequent exclusive access to the first memory address, the first subsequent exclusive access being issued prior to success of the first exclusive access and the second subsequent exclusive access being issued after success of the first exclusive access.

11. A computing system comprising:
a first plurality of processors; and
a coherence interface coupled to the first plurality of processors, the coherence interface comprising:
coherence interface storage configured to store first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of the first plurality of processors, the first state information including a proxy monitor indicator and an exclusive-write-ready indicator; and
a coherence interface state controller configured to maintain a set state of the proxy monitor indicator and a reset state of the exclusive-write-ready indicator until receiving an atomic response transaction associated with a successful colliding access of the first memory address or until detecting selection for issuance of the first exclusive access, and configured to communicate an atomic response transaction indicating a status of the first exclusive access to a coherency interconnection,
wherein the atomic response transaction is based on the first state information.

12. The computing system, as recited in claim 11 ,
wherein the coherence interface is configured to selectively forward to the first plurality of processors, a colliding exclusive access of the first memory address associated with a second reservation,
wherein the second reservation corresponds to a second exclusive access to the first memory address, and
wherein the colliding exclusive access is selectively forwarded by the coherence interface according to status information included in at least one input atomic response transaction received from the coherency interconnection.

13. The computing system, as recited in claim 11 ,
wherein the coherence interface state controller is further configured to update the first state information based on a status of a second exclusive access to the first memory address, and
wherein the second exclusive access is associated with another thread executing on a second processor of a second plurality of processors corresponding to a second coherence interface.

14. The computing system, as recited in claim 11 ,
wherein the coherence interface state controller is configured to set the proxy monitor indicator in response to the first exclusive access being a coherent access transaction and issuance of the first exclusive access by the first processor to the coherency interconnection.

15. The computing system, as recited in claim 14 , wherein the coherence interface state controller is configured to reset the proxy monitor indicator in response to a successful write to the first memory address.

16. The computing system, as recited in claim 11 ,
wherein the coherence interface state controller is configured to set the exclusive-write-ready indicator in response to the coherence interface state controller receiving an indication of performance of the first exclusive access from the coherency interconnection.

17. The computing system, as recited in claim 16 ,
wherein the coherence interface is configured to selectively forward a colliding snoop of the first memory address received from the coherency interconnection to the first plurality of processors according to a status of the exclusive-write-ready indicator.

18. The computing system, as recited in claim 16 ,
wherein the coherence interface state controller is configured to reset the exclusive-write-ready indicator in response to receiving an indication of completion of the first exclusive access.

19. The computing system, as recited in claim 11 , further comprising:
a memory;
a memory controller coupl

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Deshpande Sanjay R

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0828

  with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions · CPC title