Arithmetic and control unit, arithmetic and control method, program and parallel processor

Patent metadata

Field	Value
Publication number	US-10114639-B2
Application number	US-201715581222-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Jul 20, 2011
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

An arithmetic device which controls a parallel arithmetic operation includes a global memory, a plurality of compute units, each of the compute units including a local memory and a plurality of processing elements, and each of the processing elements including a private memory and processing data blocks stored in the private memory, an attribute group holding unit which includes a specific attribute which includes a parameter indicative of a size of the data block, an arithmetic attribute which includes a parameter indicating whether the data block is a data relevant to processing, and indicating a transfer order when the data block is data relevant to processing, and a policy attribute which includes a parameter indicative of how to execute a transfer of the data block and how to execute processing of the data block.

First claim

What is claimed is:

1. An arithmetic device which controls a parallel arithmetic operation, the arithmetic device comprising:
a global memory;
a plurality of compute units, each of the compute units including a local memory and a plurality of processing elements, and each of the processing elements including a private memory and processing data blocks stored in the private memory;
an attribute group holding unit which includes following attributes;
a specific attribute which includes a parameter indicative of a size of a data block of the data blocks;
an arithmetic attribute which includes a parameter indicating whether the data block includes data relevant to processing, and indicating a transfer order when the data block includes data relevant to processing; and
a policy attribute which includes a parameter indicative of how to execute a transfer of the data block and how to execute processing of the data block; and

a scenario determination unit that determines respective transfer systems of the data blocks between the global memory and at least one of the private memories and the local memories based on the specific attribute, the arithmetic attribute, and the policy attribute.

2. The arithmetic device according to claim 1 , wherein the scenario determination unit determines a division size of the data block and a number of iterations which includes a number of transfers necessary to transfer all divided blocks in the data block based on the specific attribute, the arithmetic attribute, and the policy attribute.

3. The arithmetic device according to claim 2 , wherein the attribute group holding unit further includes parameters representative of configuration of the arithmetic device, and the scenario determination unit determines the division size of the data blocks and the number of iterations based on the specific attribute, the arithmetic attribute, the policy attribute, and parameters representative of configuration of the arithmetic device.

4. The arithmetic device according to claim 3 , wherein the data blocks comprise read blocks and write blocks, and the read blocks are transferred from the global memory to at least one of the private memories and the local memories.

5. The arithmetic device according to claim 4 , wherein the scenario determination unit determines a transfer system of the read blocks before the processor elements executes processing and the scenario determination unit determines a transfer system of a write block after the processor element executes processing.

6. The arithmetic device according to claim 1 , wherein the arithmetic attribute comprises a read attribute which indicates whether the data block includes data to be subjected to processing or not, and the transfer order when the data is subjected to processing.

7. The arithmetic device according to claim 1 , wherein the arithmetic attribute comprises a write attribute which indicates whether the data block includes data of arithmetic results or not, and the transfer order when the data block includes data of arithmetic results.

8. The arithmetic device according to claim 4 , wherein the policy attribute comprises a margin attribute which includes a parameter indicative of the amount of data other than the divided read data block adjacent to a boundary of the divided read block.

9. The arithmetic device according to claim 4 , wherein the policy attribute comprises a broadcast attribute which includes a parameter for designating which of the private memory and the local memory is designated of the divided read block in each of the read blocks and a designation of the divided write blocks in each of the write blocks.

10. The arithmetic device according to claim 4 , wherein the policy attribute comprises an allocation attribute which includes a parameter representative of an allocation system of how the divided read blocks and the divided write blocks are allocated to the private memory group or the local memory.

11. The arithmetic device according to claim 1 , wherein the policy attribute comprises a hierarchy attribute which includes a number of hierarchy designated by a natural number 1 or more.

12. The arithmetic device according to claim 1 , wherein the policy attribute comprises a dependency attribute which includes a parameter representative of a data dependency relationship between the divided block and eight other divided blocks adjacent to the divided data block.

13. The arithmetic device according to claim 1 , wherein the arithmetic device includes an OpenCL (open computing language) device, and the attributes stored in the attribute group holding unit are set as an argument of a Kernel.

Assignees

• Renesas Electronics Corp

Inventors

• Kyo Shorin

Classifications

• G06F17/11

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