Pressure sensor and a method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10113928-B2
Application number	US-201615234911-A
Country	US
Kind code	B2
Filing date	Aug 11, 2016
Priority date	Feb 23, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

Provided is a pressure sensor including a substrate having a cavity therein, a partition wall disposed in the substrate to surround the cavity, a substrate insulation layer disposed on the top surface of the substrate to cover the cavity, a sensing unit disposed on the substrate insulation layer, and an encapsulation layer disposed on the substrate insulation layer to cover the sensing unit. The cavity may extend from a top surface toward a bottom surface of the substrate, the partition wall may have an inner sidewall exposed by the cavity, and at least a portion of the sensing unit may overlap the cavity when viewed in a plan view.

First claim

What is claimed is:

1. A pressure sensor comprising:
a substrate having a cavity therein, wherein the cavity extends from a top surface toward a bottom surface of the substrate;
a partition wall disposed in the substrate to surround the cavity, wherein the partition wall has an inner sidewall exposed by the cavity;
a substrate insulation layer disposed on the top surface of the substrate to cover the cavity;
a sensing unit disposed on the substrate insulation layer, wherein, when viewed in a plan view, at least a portion of the sensing unit overlaps the cavity; and
an encapsulation layer disposed on the substrate insulation layer to cover the sensing unit.

2. The pressure sensor of claim 1 , wherein the substrate insulation layer is connected to the partition wall to form one body.

3. The pressure sensor of claim 1 , wherein the partition wall has a bottom surface lower than that of the cavity.

4. The pressure sensor of claim 1 , wherein the sensing unit comprises a resistor.

5. The pressure sensor of claim 4 , wherein the sensing unit is provided in plurality,
the plurality of sensing units comprise first to fourth resistors contacting a top surface of the substrate insulation layer and arranged along a perimeter of the cavity,
the first and third resistors face each other in a first direction, and the second and fourth resistors face each other in a second direction crossing the first direction, and
the first and third resistors comprise sensing resistors, and the second and fourth resistors comprise reference resistors.

6. The pressure sensor of claim 4 , further comprising a protective layer disposed between the substrate insulation layer and the encapsulation layer to cover the sensing unit,
wherein the encapsulation layer extends into a through-hole passing through the substrate insulation layer and the protective layer over the cavity.

7. The pressure sensor of claim 1 , wherein the sensing unit comprises:
a reference electrode disposed on the substrate insulation layer; and
a sensing electrode spaced apart from and disposed over the reference electrode, the sensing electrode being electrically insulated from the reference electrode,
wherein a gap region is provided between the reference electrode and the sensing electrode over the cavity.

8. The pressure sensor of claim 7 , wherein the gap region is connected to the cavity through a first through-hole passing through the substrate insulation layer and the reference electrode, and
the encapsulation layer extends into a second through-hole passing through the sensing electrode over the cavity.

9. The pressure sensor of claim 8 , wherein the first through-hole has a diameter greater than that of the second through-hole.

10. The pressure sensor of claim 1 , wherein, when viewed in a plan view, the partition wall has a circular ring shape, an oval ring shape, or a ring shape having a triangular or more polygonal shape.

11. A method for manufacturing a pressure sensor, the method comprising:
etching a substrate to form a trench having a closed loop when viewed in a plan view;
forming an insulation film filled into the trench and covering a top surface of the substrate;
forming a sensing unit on the insulation film;
forming a cavity in the substrate; and
forming an encapsulation layer covering the sensing unit on the substrate in which the cavity is formed,
wherein one portion of the insulation film in the trench is defined as a partition wall, and
the forming of the cavity in the substrate comprises removing a portion of the substrate, which is surrounded by the partition wall.

12. The method for claim 11 , wherein the other portion of the insulation film covering the top surface of the substrate is defined as a substrate insulation layer, and
the forming of the sensing unit comprises:
depositing a piezo-resistive material on the substrate insulation layer; and
patterning the deposited piezo-resistive material to form a resistor.

13. The method for claim 12 , wherein, before the forming of the cavity, the method further comprises:
forming a protective layer covering the sensing unit on the substrate insulation layer; and
etching the substrate insulation layer and the protective layer to form a through-hole exposing the one portion of the substrate.

14. The method for claim 11 , wherein the other portion of the insulation film covering the top surface of the substrate is defined as a substrate insulation layer, and
the forming of the sensing unit comprises:
forming a reference electrode on the substrate insulation layer;
etching the reference electrode and the substrate insulation layer to form a first through-hole exposing the one portion of the substrate;
forming a sacrificial layer filled into the first through-hole on the reference electrode;
forming a sensing electrode covering the sacrificial layer;
forming a second through-hole passing through the sensing electrode to expose the sacrificial layer; and
removing the sacrificial layer through the second through-hole.

15. The method for claim 11 , wherein the removing of the one portion of the substrate uses a wet etching process.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Je Chang Han
• Yang Woo Seok
• Lee Sung Q
• Choi Chang Auck

Classifications

• G01L9/0054 Primary

  integral with a semiconducting diaphragm · CPC title

• G01L9/0045

  Diaphragm associated with a buried cavity · CPC title