Fully integrated wake-up receiver

Patent metadata

Field	Value
Publication number	US-10111173-B2
Application number	US-201615164667-A
Country	US
Kind code	B2
Filing date	May 25, 2016
Priority date	Jun 19, 2015
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

An apparatus is provided which comprises: a mixer to mix a first signal of a first frequency with a second signal of a second frequency, and to generate a first output; a switched-capacitor multiplier, coupled to the mixer, to receive the first output and to provide a second output with reduced noise; and an amplifier, coupled to the switched-capacitor multiplier, to amplify the second output.

First claim

We claim:

1. An apparatus comprising:
a mixer to mix a first signal of a first frequency with a second signal of a second frequency, and to generate a first output;
a switched-capacitor multiplier coupled to the mixer, wherein the switched-capacitor multiplier is to receive the first output and to provide a second output with reduced noise; and
an amplifier coupled to the switched-capacitor multiplier, wherein the amplifier is to amplify the second output.

2. The apparatus of claim 1 comprises an impedance matching network having an impedance matched with an impedance of an antenna, wherein the impedance matching network is coupled to the mixer and is to provide the first signal to the mixer.

3. The apparatus of claim 1 , wherein the mixer is a passive mixer.

4. The apparatus of claim 1 comprises a clock source to provide the second signal to the mixer and to provide a third signal of a third frequency to the switched-capacitor multiplier.

5. The apparatus of claim 4 , wherein the clock source is one of a frequency locked loop (FLL) or a phase locked loop (PLL).

6. The apparatus of claim 1 comprises a filter coupled to the amplifier, wherein the filter is to filter a portion of the second output to detect a wakeup signal.

7. The apparatus of claim 1 comprises a filter integrated with the amplifier, wherein the filter is to filter a portion of the second output to detect a wakeup signal.

8. The apparatus of claim 6 comprises an analog-to-digital converter (ADC) coupled to the filter, wherein the ADC is to convert the filtered portion of the second output to a digital representation.

9. The apparatus of claim 8 comprises:
an envelope detector coupled to the ADC;
a digital decimator and accumulator coupled to the envelope detector; and
a decision circuit coupled to the digital decimator and accumulator, wherein the decision circuit is to generate a control signal according to whether a wakeup signal is detected.

10. The apparatus of claim 1 comprises a low noise amplifier (LNA) coupled to the mixer, wherein the LNA is to provide the first signal to the mixer.

11. The apparatus of claim 8 comprises a baseband logic coupled to the ADC.

12. The apparatus of claim 11 , wherein the baseband logic comprises:
an envelope detector coupled to the ADC;
a digital decimator and accumulator coupled to the envelope detector; and
a decision circuit coupled to the digital decimator and accumulator, wherein the decision circuit is to generate a control signal according to whether a wakeup signal is detected.

Assignees

• Intel Corp

Inventors

• Alpman Erkan
• Khairi Ahmad B
• Pellerano Stefano
• Ravi Ashoke

Classifications

• Y02D70/1262

  Cross-Sectional Technologies · mapped topic

• Y02D70/144

  Cross-Sectional Technologies · mapped topic

• Y02D70/142

  Cross-Sectional Technologies · mapped topic

• Y02D70/162

  Cross-Sectional Technologies · mapped topic

• Y02D70/21

  Cross-Sectional Technologies · mapped topic