Apparatus and methods for calibrating analog circuitry in an integrated circuit

Patent metadata

Field	Value
Publication number	US-10110328-B2
Application number	US-201213446555-A
Country	US
Kind code	B2
Filing date	Apr 13, 2012
Priority date	Apr 13, 2012
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

First claim

What is claimed is:

1. A method of calibrating analog circuitry within an integrated circuit, the method comprising:
booting up a microcontroller that is embedded in the integrated circuit by loading boot code from a programmer object file to a memory of the microcontroller residing in the microcontroller, and resetting the microcontroller;
sending a reset control signal to reset an analog circuit in the integrated circuit;
monitoring a response signal of the analog circuit by the microcontroller;
determining a calibration parameter for the analog circuit based on the response signal; and
configuring the analog circuit using the calibration parameter, wherein the sending, monitoring, determining, and configuring is performed by the microcontroller in response to executing the boot code in the memory of the microcontroller.

2. The method of claim 1 , wherein a common bus couples the microcontroller to a plurality of analog circuits to be calibrated.

3. The method of claim 1 , wherein the response signal for the analog circuit is generated in response to variation of a control parameter of the analog circuit.

4. The method of claim 1 , wherein the response signal of the analog circuit is communicated to the microcontroller using a shift register.

5. The method claim 1 further comprising:
communicating a signal from the microcontroller to a core of the integrated circuit, the signal indicating that calibration of the analog circuit is complete.

6. The method of claim 1 further comprising:
repeating the sending, monitoring, determining, and configuring for a plurality of analog circuits.

7. The method of claim 6 , wherein the plurality of analog circuits include comparators, phase detectors, sense amplifiers, voltage controlled oscillators, and voltage regulators.

8. The method of claim 7 , wherein for the phase detector, the response signal is a test data signal, and the calibration parameter determines an amount of offset cancellation.

9. The method claim 6 further comprising:
communicating a signal from the microcontroller to a core of the integrated circuit, the signal indicating that calibration of the plurality of analog circuits is complete.

10. The method of claim 1 , wherein the reset control signal is sent to a plurality of analog circuits of a same type in the integrated circuit such that calibration related processes for the plurality of analog circuits proceed in parallel, further comprising waiting to receive response signals for the plurality of analog circuits, wherein a response signal for an individual analog circuit is received after a calibration related process for the individual analog circuit is done.

11. The method of claim 10 , wherein, after the response signal for the individual analog circuit is received, the method further comprises:
configuring the individual analog circuit;
determining if all analog circuits of the plurality of analog circuits have been configured; and
waiting to receive further response signals if not all of the plurality of analog circuits have been configured.

12. The method of claim 1 , wherein when the analog circuit is a voltage controlled oscillator, the calibration parameter determines one of a receiving and transmitting frequency.

13. A system for calibrating analog circuits within an integrated circuit, the system comprising:
a core of the integrated circuit;
a microcontroller that is embedded in the integrated circuit, the microcontroller including a processing unit and memory;
a plurality of sub-modules that includes the analog circuits therein;
a communication system arranged to communicatively interconnect the microcontroller with the plurality of sub-modules for calibration of the analog circuits therein; and
a tangible non-transitory storage medium for storing boot code for the microcontroller, wherein the boot code is loaded to the memory of the microcontroller from a programmer object file in the tangible non-transitory storage medium, and wherein the microcontroller configures the analog circuits in response to executing the boot code in the memory of the microcontroller.

14. The system of claim 13 , wherein the boot code comprises:
computer-readable program instructions for sending a reset control signal to a sub-module of the plurality of sub-modules to reset an analog circuit in the sub-module;
computer-readable program instructions for monitoring the communication system for a response signal from the sub-module;
computer-readable program instructions for determining a calibration parameter for the analog circuit in the sub-module based on the response signal; and
computer-readable program instructions for configuring the analog circuit in the sub-module using the calibration parameter.

15. The system of claim 14 , wherein the boot code further comprises:
computer-readable program instructions for repeating the sending, monitoring, determining, and configuring for further sub-modules of the plurality of sub-modules; and
computer-readable program instructions for communicating a signal from the microcontroller to the core of the integrated circuit, the signal indicating that calibration of the analog circuits in the plurality of sub-modules is complete.

16. The system of claim 14 , wherein the boot code further comprises:
computer-readable program instructions for sending a reset control signal to the plurality of sub-modules such that calibration-related processes for the plurality of submodules proceed in parallel;
computer-readable program instructions for waiting to receive response signals from the plurality of sub-modules, wherein a response signal for an individual submodule is received after an analog calibration-related process for the individual submodule is complete;
computer-readable program instructions for configuring the individual submodule after the response signal from the individual sub-module is received;
computer-readable program instructions for determining if all of the plurality of sub-modules have been configured; and
computer-readable program instructions for waiting to receive further response signals if not all of the plurality of sub-modules have been configured.

17. The system of claim 14 , wherein the boot code further comprises:
computer-readable program instructions for repeating the sending, monitoring, determining, and configuring for further sub-modules of the plurality of sub-modules.

18. The system of claim 14 , wherein the boot code further comprises:
computer-readable program instructions for sending a reset control signal to the plurality of sub-modules such that calibration-related processes for the plurality of submodules proceed in parallel.

19. The system of claim 14 , wherein the communication system comprises:
a common bus arranged to communicatively interconnect the microcontroller with the plurality of sub-modules for calibration of the analog circuits; and
interface circuitry arranged between the common bus and the plurality of submodules, wherein the interface circuitry includes a shift register to communicate test data from the plurality of sub-modules to the common bus, a shift register to communicate calibration control signals from the common bus to the plurality of sub-modules, and a reset control circuit to controllably reset an analog circuit within the sub-modules.

20. The system of claim 19 , wherein the interface circuitry further includes a memory-mapped port for addressing the plurality of sub-modules by way of the common bus.

Assignees

• Carvalho Neville
• Hoang Tim Tri
• Shumarayev Sergey
• Altera Corp

Inventors

• Carvalho Neville
• Hoang Tim Tri
• Shumarayev Sergey

Classifications

• H04B17/22 Primary

  for calibration of the receiver components · CPC title

• H04B17/21 Primary

  for calibration; for correcting measurements · CPC title

• G01R35/005

  Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references (G01R33/0035, G01R35/002 take precedence) · CPC title

• G01R35/00

  Testing or calibrating of apparatus covered by the other groups of this subclass · CPC title

• G12B13/00

  Calibrating of instruments and apparatus (calibrating of measuring instruments G01) · CPC title