Voltage comparator circuit including a plurality of voltage controlled delay lines

Patent metadata

Field	Value
Publication number	US-10110214-B2
Application number	US-201715403631-A
Country	US
Kind code	B2
Filing date	Jan 11, 2017
Priority date	Jan 11, 2017
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

An embodiment circuit includes a first voltage-controlled delay line (VCDL), a second VCDL, and a first flip-flop. The first VCDL includes a first input terminal configured to receive a first input voltage, and a second input terminal configured to receive a clock signal. The second VCDL includes a first input terminal configured to receive a second input voltage, and a second input terminal configured to receive the clock signal. The first flip-flop includes a reset pin coupled to an output terminal of the first VCDL, and a clock pin coupled to an output terminal of the second VCDL.

First claim

What is claimed is:

1. A circuit, comprising:
a first voltage-controlled delay line (VCDL) comprising a first input terminal configured to receive a first input voltage, and a second input terminal configured to receive a clock signal;
a second VCDL comprising a first input terminal configured to receive a second input voltage, and a second input terminal configured to receive the clock signal;
a first flip-flop comprising a reset pin coupled to an output terminal of the first VCDL, and a clock pin coupled to an output terminal of the second VCDL;
a second flip-flop having a data input pin coupled to an output pin of the first flip-flop; and
a third flip-flop having a data input pin and a reset pin configured to receive an enable signal, a clock pin configured to receive the clock signal, and an output pin coupled to a reset pin of the second flip-flop.

2. The circuit of claim 1 , wherein the first VCDL is configured to generate a first delayed pulse at the output terminal of the first VCDL in response to the first input voltage, wherein a rising edge of the first delayed pulse is delayed in time relative to a rising edge of the clock signal.

3. The circuit of claim 2 , wherein a falling edge of the first delayed pulse is temporally aligned with a falling edge of the clock signal.

4. The circuit of claim 2 , wherein a delay between the rising edge of the first delayed pulse and the rising edge of the clock signal is inversely proportional to an amplitude of the first input voltage.

5. The circuit of claim 1 , wherein the second VCDL is configured to generate a second delayed pulse at the output terminal of the second VCDL in response to the second input voltage, wherein a rising edge of the second delayed pulse is delayed in time relative to a rising edge of the clock signal.

6. The circuit of claim 5 , wherein a delay between the rising edge of the second delayed pulse and the rising edge of the clock signal is inversely proportional to an amplitude of the second input voltage.

7. The circuit of claim 1 , wherein the first flip-flop is configured to generate an output voltage in response to a difference between the first input voltage and the second input voltage.

8. The circuit of claim 7 , wherein the output voltage of the first flip-flop is at a first logical value in response to the first input voltage being greater than the second input voltage, and wherein the output voltage of the first flip-flop is at a second logical value in response to the first input voltage being less than the second input voltage.

9. The circuit of claim 1 , wherein the first flip-flop further comprises a data input pin configured to receive a constant input logical value.

10. A circuit, comprising:
a first voltage-controlled delay line (VCDL) comprising:
a first inverter having an input configured to receive a clock signal, and a first power terminal configured to be coupled to a first supply voltage;
a second inverter having an input coupled to an output of the first inverter, a first power terminal configured to be coupled to the first supply voltage, and a second power terminal configured to be coupled to a ground potential;
a first capacitive element coupled between an output of the first inverter and the ground potential;
a first current source coupled between a second power terminal of the first inverter and the ground potential, wherein the first current source is configured to be controlled by a first input voltage; and
a first switch coupled between the first supply voltage and the second power terminal of the first inverter, wherein the first switch is configured to be controlled by the clock signal, and wherein an output of the second inverter is an output of the first VCDL.

11. The circuit of claim 10 , further comprising:
a second VCDL comprising:
a third inverter having an input configured to receive the clock signal, and a first power terminal configured to be coupled to the first supply voltage;
a fourth inverter having an input coupled to an output of the third inverter, a first power terminal configured to be coupled to the first supply voltage, and a second power terminal configured to be coupled to the ground potential;
a second capacitive element coupled between an output of the third inverter and the ground potential;
a second current source coupled between a second power terminal of the third inverter and the ground potential, wherein the second current source is configured to be controlled by a second input voltage; and
a second switch coupled between the first supply voltage and the second power terminal of the third inverter, wherein the second switch is configured to be controlled by the clock signal, and wherein an output of the fourth inverter is an output of the second VCDL.

12. The circuit of claim 11 , wherein at least one of the first capacitive element or the second capacitive element comprises a programmable capacitor.

13. The circuit of claim 11 , further comprising a first flip-flop having a reset pin coupled to the output of the second inverter, and a clock pin coupled to the output of the fourth inverter.

14. The circuit of claim 13 , further comprising a second flip-flop having a data input pin coupled to an output pin of the first flip-flop.

15. The circuit of claim 14 , further comprising a third flip-flop having a data input pin and a reset pin configured to receive an enable signal, a clock pin configured to receive the clock signal, and an output pin coupled to a reset pin of the second flip-flop.

16. A method, comprising:
delaying, by a first voltage-controlled delay line (VCDL), a rising edge of a clock signal by a first time delay based on a first input voltage received at the first VCDL, wherein the delaying produces a first delayed signal;
delaying, by a second VCDL, the rising edge of the clock signal by a second time delay based on a second input voltage received at the second VCDL, wherein the delaying produces a second delayed signal;
triggering a reset pin of a first flip-flop using the first delayed signal;
triggering a clock pin of the first flip-flop using the second delayed signal;
sampling, using a data pin of a second flip-flop, an output of the first flip-flop;
triggering a clock pin of a third flip-flop using the clock signal;
triggering a reset pin and a data input pin of the third flip-flop using an enable signal; and
triggering a reset pin of the second flip-flop using an output of the third flip-flop.

17. The method of claim 16 , wherein the output of the first flip-flop is at a first logical value in response to the first input voltage being greater than the second input voltage, and wherein the output of the first flip-flop is at a second logical value in response to the first input voltage being less than the second input voltage.

18. The method of claim 16 , further comprising:
providing a constant voltage to a data input pin of the first flip-flop.

19. The method of claim 16 , wherein the first time delay and the second time delay are inversely proportional to an amplitude of the first input voltage and an amplitude of the second input voltage, respectively.

20. The method of claim 16 , further comprising:
generating the clock signal by delaying and inverting a buffered clock signal; and
triggering a clock pin of the second flip-flop using the buffered clock signal.

Assignees

• St Microelectronics Res & Dev Ltd

Inventors

• Zhuang Caixin

Classifications

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K5/249

  using clock signals · CPC title

• H03K2005/00019

  Variable delay · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K2005/00045

  DC voltage control of a capacitor or of the coupling of a capacitor as a load · CPC title