Package integrated with a power source module

US10109602B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10109602-B2
Application numberUS-201615279973-A
CountryUS
Kind codeB2
Filing dateSep 29, 2016
Priority dateMar 16, 2016
Publication dateOct 23, 2018
Grant dateOct 23, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A package integrated with a power source module may be provided. The package including a substrate having an upper surface and a lower surface, a chip on the upper surface of the substrate, a first power supply on the upper surface of the substrate, the first power supply at one side of the chip, an encapsulant encapsulating the chip and the first power supply, a second power supply on the encapsulant, the second power supply electrically connected with the substrate through a connection member, the connection member penetrating through the encapsulant may be provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A package comprising: a substrate having an upper surface and a lower surface; a chip on the upper surface of the substrate; a first power supply on the upper surface of the substrate, the first power supply at one side of the chip, the first power supply including a magnetic resonance element; an encapsulant encapsulating the chip and the first power supply; and a second power supply on the encapsulant, the second power supply electrically connected with the substrate through a connection member, the connection member penetrating through the encapsulant. 2. The package of claim 1 , wherein the magnetic resonance element includes a magnetic thin film and a coil surrounding the magnetic thin film. 3. The package of claim 1 , wherein the second power supply includes a thin film solar energy module. 4. The package of claim 1 , wherein the connection member includes metal. 5. The package of claim 1 , wherein the package further includes: a passive device on the upper surface of the substrate. 6. The passive device of claim 5 , wherein the passive device includes at least one of a capacitor, a resistor, or an inductor. 7. The package of claim 1 , wherein the package further includes: a passive device buried in the substrate. 8. The package of claim 1 , wherein the chip includes: at least one function chip and a power processing chip that are stacked on the upper surface of the substrate. 9. The package of claim 8 , wherein the at least one function chip includes one or more of a processor, a memory, and a communication module. 10. A semiconductor package comprising: a substrate having an upper surface and a lower surface; a semiconductor chip on the upper surface of the substrate; a first power supply on the upper surface of the substrate, the first power supply configured to supply power from an external power source, the first power supply including a magnetic resonance element; an encapsulant encapsulating the semiconductor chip and the first power supply; and a self-powered power supply on the encapsulation, the self-powered power supply configured to supply power to the semiconductor chip via a conductive connection member penetrating through the encapsulant and the substrate. 11. The semiconductor package of claim 10 , wherein the magnetic resonance element includes a magnetic thin film and a coil surrounding the magnetic thin film. 12. The semiconductor package of claim 10 , wherein the self-powered power supply includes a solar energy module. 13. The semiconductor package of claim 10 , wherein the self-powered power supply includes a thin film solar energy module, and the thin film solar energy module includes an amorphous silicon layer with a PIN structure. 14. The semiconductor package of claim 10 , wherein the conductive connection member includes metal.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between stacked chips · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • by a substrate and the encapsulations · CPC title

  • Forming coatings · CPC title

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Frequently asked questions

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What does patent US10109602B2 cover?
A package integrated with a power source module may be provided. The package including a substrate having an upper surface and a lower surface, a chip on the upper surface of the substrate, a first power supply on the upper surface of the substrate, the first power supply at one side of the chip, an encapsulant encapsulating the chip and the first power supply, a second power supply on the enca…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W42/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 23 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).