Method of cleaning wafer after CMP

Patent metadata

Field	Value
Publication number	US-10109523-B2
Application number	US-201615395057-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Nov 29, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

First claim

What is claimed is:

1. A method comprising:
forming a first dielectric layer over a wafer;
etching the first dielectric layer to form a first opening;
filling a tungsten-containing material into the first opening;
performing a first Chemical Mechanical Polish (CMP) on the wafer;
after the CMP, performing a first cleaning on the wafer using a weak base solution; and
forming a second dielectric layer over and contacting the tungsten-containing material, wherein a carbon-rich layer is formed between, and is in contact with, the tungsten-containing material and the second dielectric layer.

2. The method of claim 1 , wherein the weak base solution comprises an organic amine.

3. The method of claim 2 , wherein the organic amine comprises C 5 H 15 NO 2 .

4. The method of claim 2 , wherein a PH value of the weak base solution is in a range between 7.0 and about 8.0.

5. The method of claim 1 further comprising forming a source/drain region, wherein a portion of the tungsten-containing material left after the CMP acts as a contact plug, and the contact plug is electrically coupled to the source/drain region.

6. The method of claim 1 further comprising:
forming a third dielectric layer over the first dielectric layer;
etching the third dielectric layer to form a second opening, wherein the second opening is wider than the first opening;
filling a second tungsten-containing material into the second opening;
performing a second CMP on the wafer; and
after the second CMP, performing a second cleaning on the wafer using an acidic solution or a neutral liquid.

7. The method of claim 1 , wherein the carbon-rich layer does not extend directly on the first dielectric layer.

8. A method comprising:
forming an Inter-layer Dielectric (ILD) with a portion at a same level as a gate stack of a transistor, wherein the ILD and the gate stack are parts of a wafer;
etching the ILD to form a source/drain contact opening, wherein a source/drain region of the transistor is exposed through the source/drain contact opening;
depositing a first tungsten-containing material on the wafer, wherein the first tungsten-containing material comprises a portion filling the source/drain contact opening;
performing a Chemical Mechanical Polish (CMP) on the wafer to remove excess portions of the first tungsten-containing material;
cleaning the wafer using a cleaning solution comprising organic amine, wherein the cleaning solution is a weak base solution having a PH value in a range greater than 7.0 and smaller than about 8.0;
drying the wafer; and
forming a dielectric layer over and contacting the first tungsten-containing material, wherein a carbon-rich layer is formed between, and is in contact with, the first tungsten-containing material and the dielectric layer.

9. The method of claim 8 , wherein from a first time point the CMP is finished to a second time point the wafer is fully dried, no neutral liquid is used for cleaning the wafer.

10. The method of claim 9 , wherein from a first time point the CMP is finished to a second time point the wafer is fully dried, no acid solution is used for cleaning the wafer.

11. The method of claim 8 , wherein the organic amine comprises C 5 H 15 NO 2 .

12. The method of claim 8 further comprising:
filling a second tungsten-containing material into an additional opening in the wafer, wherein the addition opening is wider than the source/drain contact opening;
performing an additional CMP on the wafer to remove excess portions of the second tungsten-containing material outside the additional opening; and
after the additional CMP, cleaning the wafer using an acidic solution or a neutral liquid.

13. The method of claim 8 further comprising adding a buffer agent into the cleaning solution to stabilize a PH value in the cleaning solution.

14. The method of claim 8 , wherein the carbon-rich layer does not extend onto top surfaces of the dielectric layer.

15. The method of claim 12 , wherein the cleaning the wafer after the additional CMP is performed using a neutral liquid.

16. A method comprising:
forming a source/drain contact opening in a dielectric layer of a wafer;
filling the source/drain contact opening with tungsten;
performing a Chemical Mechanical polish (CMP) to remove excess portions of the tungsten, wherein a remaining portion of the tungsten forms a portion of a source/drain contact plug;
cleaning the wafer using a cleaning solution comprising C 5 H 15 NO 2 ; and
drying the wafer, wherein from a first time point the CMP is finished to a second time point the wafer is dried, all solutions used for cleaning the wafer have PH values in a range between 7.0 and about 8.0, and wherein after the drying the wafer, a carbon-rich layer exists at a top surface of the source/drain contact plug.

17. The method of claim 16 , wherein the cleaning solution comprises a buffer solution and water.

18. The method of claim 16 , wherein at a time the drying the wafer is started, a recess is generated, with the recess extending from a top surface of the dielectric layer to a top surface of the source/drain contact plug, and the recess has a depth smaller than about 50 Å.

19. The method of claim 16 , wherein the CMP is performed with the cleaning solution being sprayed on the wafer for a duration between about 1.5 minutes and about 2.5 minutes.

20. The method of claim 16 , wherein the carbon-rich layer does not extend directly on a top surface of the dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chung Chien-Hao
• Lin Chang-Sheng
• Huang Kuo-Feng
• Wu Li-Chieh
• Lin Chun-Chieh

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P70/277

  the processing being a planarisation of conductive layers · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title