Double bias memristive dot product engine for vector processing

Patent metadata

Field	Value
Publication number	US-10109348-B2
Application number	US-201415522364-A
Country	US
Kind code	B2
Filing date	Oct 30, 2014
Priority date	Oct 30, 2014
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.

First claim

What is claimed is:

1. A double bias memristive dot-product system for vector processing, comprising:
a crossbar array comprising N row electrodes, M column electrodes and N×M memory elements, the memory elements positioned at the intersections between the N row electrodes and the M column electrodes of the crossbar array, each memory element comprising a memristive storage device;
a first vector input register to supply first voltage inputs to each of the N row electrodes;
a second vector input register to supply second voltage inputs to each of the N row electrodes;
a vector output register to receive voltage outputs from each of the M column electrodes,
wherein the first vector input register is connected to each of the N row electrodes at a j th column (j=1,M) and the second vector input register is connected to each of the N row electrodes at a k th column (k≠j), and
wherein the vector output register is connected to each of the M column electrodes at a row i=N, and
a second vector output register to receive voltage outputs from each of the M column electrodes and in which the second vector output register is connected to each of the M column electrodes at a row i=1.

2. The system of claim 1 , in which the first vector input register is connected to each of the N row electrodes at a j=1 column and the second vector input register is connected to each of the N row electrodes at a j=M column.

3. A double bias dot-product engine for vector processing, comprising:
a crossbar array comprising N×M memory elements corresponding to values contained in an N×M matrix, the memory elements positioned at the intersections between N row electrodes and M column electrodes, each memory element comprising a memristive storage device;
a first vector input register comprising N voltage inputs, each voltage input corresponding to a value contained in a vector having N values, connected to the crossbar array to supply first voltage inputs to each of the N row electrodes;
a second vector input register comprising N voltage inputs, each voltage input corresponding to the values contained in the vector having N values, connected to the crossbar array to supply second voltage inputs to each of the N row electrodes;
a first vector output register to receive voltage outputs from each of the M column electrodes, and
a second vector output register to receive voltage outputs from each of the M column electrodes.

4. The dot-product engine of claim 3 , in which the first vector input register is connected to each of the N row electrodes at a j=1 column and the second vector input register is connected to each of the N row electrodes at a j=M column.

5. The dot-product engine of claim 3 , in which the first vector output register is connected to each of the M column electrodes at a row i=N and the second vector output register is connected to each of the M column electrodes at a row i=1.

6. The dot-product engine of claim 3 , further comprising analog to digital converters positioned between each of the M column electrodes and the output registers of the first and second vector output registers and digital to analog converters positioned between each of the N row electrodes and the input registers of the first and second vector input registers.

7. A method for vector-processing using a crossbar array, comprising:
providing a crossbar array comprising N×M memory elements, the memory elements positioned at the intersections between N row electrodes and M column electrodes, each memory element comprising a memristive storage device; a first vector input register to supply first voltage inputs to each of the N row electrodes; a second vector input register to supply second voltage inputs to each of the N row electrodes; and a first vector output register to receive voltage outputs from each of the M column electrodes;
setting memristance values at the N×M memory locations within the crossbar array, the memristance values corresponding to row and column values of an N×M matrix;
setting input voltages corresponding to values of an N×1 matrix;
applying a voltage input at two locations on each of the N row electrodes;
determining output voltages at the M voltage outputs, each output voltage corresponding to a row and column multiplication of the N×M matrix and the N×1 vector,
wherein the crossbar array further comprises a second vector output register to receive voltage outputs from each of the M column electrodes and in which the first vector output register is connected to each of the M column electrodes at a row i=N and the second vector output register is connected to each of the M column electrodes at a row i=1.

8. The method of claim 7 , in which for each of the N row electrodes, an input voltage is applied at a j=1 and j=M columns.

9. The method of claim 7 , wherein the voltage output at each of the M columns is determined by passing current outputs received at rows i=1 and i=N for each of the M columns of the crossbar array through a resistance device.

10. The method of claim 7 , wherein setting memristance values at the N×M memory locations, setting input voltages at the N voltage inputs, applying the voltage inputs and determining output voltages at the M voltage outputs is performed iteratively until a convergence criteria is satisfied.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Hu Miao
• Yang Jianhua
• Strachan John Paul
• Ge Ning

Classifications

• G11C13/0026 Primary

  Bit-line or column circuits · CPC title

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title