Memory management method and device and memory controller

Patent metadata

Field	Value
Publication number	US-10108553-B2
Application number	US-201715415344-A
Country	US
Kind code	B2
Filing date	Jan 25, 2017
Priority date	Jul 31, 2014
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.

First claim

What is claimed is:

1. A method, wherein the method is applied to a memory management device that is located in a memory controller, and the method comprises:
receiving a fetch request sent by a processor, wherein the fetch request carries a virtual address;
determining whether a translation look-aside buffer (TLB) located in the memory management device caches a page table corresponding to the virtual address carried in the fetch request;
when the TLB caches a page table corresponding to the virtual address carried in the fetch request, obtaining a physical address corresponding to the virtual address from the page table, wherein the page table comprises a correspondence between virtual addresses and physical addresses; and
when the TLB does not buffer a page table corresponding to the virtual address carried in the fetch request, performing the following:
obtaining a base address field of a page table of a process corresponding to the virtual address, and searching for the page table of the process corresponding to the virtual address according to the base address field of the page table of the process corresponding to the virtual address;
when the page table of the process corresponding to the virtual address comprises the virtual address carried in the fetch request, obtaining a physical address corresponding to the virtual address; and
when the page table of the process corresponding to the virtual address does not comprise the virtual address carried in the fetch request, determining whether the virtual address is valid, and applying for a blank page when it is determined that the virtual address is valid.

2. The method according to claim 1 , further comprising:
when the application for the blank page succeeds, starting memory reading and writing; and
when the application for the blank page fails, selecting a replacement page and providing the replacement page to an operating system so that the operating system replaces a page.

3. The method according to claim 2 , wherein after the application for the blank page succeeds, the method further comprises:
updating the page table of the process corresponding to the virtual address so that the page table of the process corresponding to the virtual address comprises the virtual address carried in the fetch request, and saving the page table of the process corresponding to the virtual address to the TLB.

4. The method according to claim 1 , wherein determining whether the virtual address is valid comprises:
determining whether the virtual address falls within an allocated virtual address space;
when the virtual address falls within the allocated virtual address space, determining that the virtual address is valid; and
when the virtual address does not fall within the allocated virtual space, finding whether the virtual address exists in a virtual memory address (VMA) space, and if the virtual address exists in the VMA space, determining that the virtual address is valid.

5. The method according to claim 1 , wherein before applying for the blank page, the method further comprises:
counting a frequency of use of each cached blank page in a preset period; and
selecting a blank page having a lowest frequency of use in the preset period when applying for the blank page.

6. The method according to claim 1 , wherein it is found that the page table of the process corresponding to the virtual address comprises the virtual address carried in the fetch request, and before obtaining the physical address corresponding to the virtual address, the method further comprises:
saving the page table of the process corresponding to the virtual address to the TLB.

7. A device, wherein the device is located in a memory controller, and the device comprises:
a translation look-aside buffer (TLB);
a memory management unit (MMU); and
a microcontroller;
wherein the TLB is configured to:
receive a fetch request sent by a processor, wherein the fetch request carries a virtual address, and determine whether the TLB caches a page table corresponding to the virtual address carried in the fetch request; and
when the TLB caches a page table corresponding to the virtual address carried in the fetch request, obtain a physical address corresponding to the virtual address from the page table, wherein the page table comprises a correspondence between virtual addresses and physical addresses;

wherein the MMU is configured to:
when the TLB does not cache a page table corresponding to the virtual address carried in the fetch request, obtain a base address field of a page table of a process corresponding to the virtual address and search for the page table of the process corresponding to the virtual address according to the base address field of the page table of the process corresponding to the virtual address; and

when the page table of the process corresponding to the virtual address comprises the virtual address, obtain a physical address corresponding to the virtual address; and
wherein the microcontroller is configured to:
when the page table of the process corresponding to the virtual address does not comprise the virtual address, determine whether the virtual address is valid, and when it is determined that the virtual address is valid, apply for a blank page.

8. The device according to claim 7 , wherein the microcontroller is further configured to:
when the application for the blank page succeeds, start memory reading and writing; and
when the application for the blank page fails, select a replacement page and provide the replacement page to an operating system, so that the operating system replaces a page.

9. The device according to claim 7 , wherein the microcontroller is further configured to:
determine whether the virtual address falls within an allocated virtual address space;
when the virtual address falls within an allocated virtual address space, determine that the virtual address is valid; or
when the virtual address does not fall within an allocated virtual address space, find whether the virtual address exists in a virtual memory address (VMA) space, and when the virtual address exists in the VMA space, determine that the virtual address is valid.

10. The device according to claim 7 , wherein the microcontroller is further configured to:
receive the fetch request;
obtain the base address field of the page table of the process corresponding to the virtual address carried in the fetch request; and
send the base address field of the page table of the process corresponding to the virtual address to the MMU, so that the MMU searches for the page table of the process corresponding to the virtual address according to the base address field of the page table of the process corresponding to the virtual address.

11. The device according to claim 7 , wherein the microcontroller is further configured to: count a frequency of use of each cached blank page in a preset period, and select a blank page having a lowest frequency of use in the preset period when applying for the blank page.

12. A memory controller, comprising the device according to claim 7 .

Assignees

• Huawei Tech Co Ltd

Inventors

• Liu Yao
• Chen Licheng
• Cui Zehan
• Chen Mingyu

Classifications

• G06F2212/681

  Multi-level TLB, e.g. microTLB and main TLB · CPC title

• G06F2212/684

  TLB miss handling · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title