Systems and methods for network routing in small-world network-on-chip devices

Patent metadata

Field	Value
Publication number	US-10103913-B2
Application number	US-201615081524-A
Country	US
Kind code	B2
Filing date	Mar 25, 2016
Priority date	Mar 25, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

In some embodiments, improved routing strategies for small-world network-on-chip (SWNoC) systems are provided. In some embodiments, an ALASH routing strategy or an MROOTS strategy are used in order to improve latency, temperature, and energy use within a network-on-chip system. In some embodiments, millimeter-wave wireless transceivers are used to implement the long-distance links within the small-world network, to create a millimeter-wave small-world network-on-chip (mSWNoC) system. In some embodiments, non-coherent on-off keying (OOK) wireless transceivers are used to implement the wireless links.

First claim

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An integrated circuit, comprising:
a plurality of processing cores; and
a plurality of switches connected to the plurality of processing cores;
wherein at least two switches of the plurality of switches include non-coherent on-off keying (OOK) wireless transceivers for establishing a wireless communication link between the at least two switches; and
wherein each of the non-coherent OOK wireless transceivers comprises a receiver having a wideband low-noise amplifier, an envelope detector for non-coherent demodulation, and a baseband amplifier.

2. The integrated circuit of claim 1 , wherein the receiver does not include a local oscillator.

3. The integrated circuit of claim 1 , wherein each of the non-coherent OOK wireless transceivers comprises a transmitter having an OOK modulator, a voltage-controlled oscillator, and a wideband power amplifier.

4. The integrated circuit of claim 1 , wherein each of the non-coherent OOK wireless transceivers is coupled to a zig-zag antenna.

5. The integrated circuit of claim 1 , wherein at least two switches of the plurality of switches are communicatively coupled via wireline connections.

6. The integrated circuit of claim 5 , wherein the wireless communication link and wireline connections between the switches of the plurality of switches form a network having small-world properties.

7. The integrated circuit of claim 6 , wherein information is routed within the network using an adaptive layered shortest path routing (ALASH) technique.

Assignees

• Pande Partha
• Heo Deukhyoun
• Univ Washington State

Inventors

• Pande Partha
• Heo Deukhyoun

Classifications

• H04L2012/6421

  Medium of transmission, e.g. fibre, cable, radio, satellite · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L27/04

  Modulator circuits; Transmitter circuits · CPC title

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title