Constant impedance switch

Patent metadata

Field	Value
Publication number	US-10103711-B2
Application number	US-201414297598-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jun 30, 2012
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.

First claim

What is claimed:

1. A device comprising:
a switch comprising a plurality of variable impedances configured to dynamically manage switch impedance during a first switching event by stepping a variable impedance in the plurality of variable impedances through an impedance sequence that changes the variable impedance a plurality of times to a plurality of different discrete impedance values during the first switching event to maintain the switch impedance during the first switching event, where the first switching event comprises a single state transition of the switch from a first state to a second state.

2. The device of claim 1 , the switch comprising a multi-throw switch, wherein the switch comprises:
a first path between first and third ports, the first path comprising a first variable impedance configured to be stepped through a first impedance sequence during the first switching event; and
a second path between second and third ports, the second path comprising a second variable impedance configured to be stepped through a second impedance sequence during the first switching event.

3. The device of claim 2 , wherein a first range of the first impedance sequence is different from a second range of the second impedance sequence.

4. The device of claim 2 , wherein steps in the first impedance sequence are logarithmic.

5. The device of claim 2 , wherein
the first variable impedance comprises a first series impedance and a first shunt impedance and the first impedance sequence comprises a first series impedance sequence and a first shunt impedance sequence;
the second variable impedance comprises a second series impedance and a second shunt impedance and the second impedance sequence comprises a second series impedance sequence and a second shunt impedance sequence; and
the switch further comprises:
a third variable impedance coupled between the first and second paths, the third impedance configured to be stepped through a third impedance sequence during the first switching event.

6. The device of claim 2 , wherein the first and second variable impedances comprise, respectively, first and second configurable transistor cells.

7. The device of claim 6 , wherein the first and second configurable transistor cells comprise, respectively, a first and second circuit of selectable transistors selectable to provide the first and second impedance sequences during the first switching event.

8. The device of claim 7 , wherein each selectable transistor in the first and second circuit of selectable transistors comprises a stack of transistors.

9. The device of claim 2 , the switch further comprising:
a control circuit that steps the first and second variable impedances, respectively, through the first and second impedance sequences during the first switching event and through additional impedance sequences for additional switching events to maintain switch impedance during the plurality of switching events.

10. A method comprising:
dynamically managing an impedance of a switch during a first switch event comprising a single state transition of the switch from a first state to a second state by stepping a first variable impedance in the switch through a first sequence of impedance values that changes the first variable impedance a plurality of times to a plurality of different discrete impedance values during the first switching event to maintain the impedance of the switch during the first switch event.

11. The method of claim 10 , the switch comprising a second variable impedance, wherein maintaining the impedance comprises:
maintaining the impedance of the switch during the first switch event by stepping the first and second variable impedances, respectively, through first and second sequences of impedance values.

12. The method of claim 11 , further comprising:
maintaining the impedance of the switch during a second switch event by stepping the first and second variable impedances, respectively, through third and fourth sequences of impedance values.

13. The method of claim 11 , wherein stepping the first and second variable impedances comprises:
stepping the first and second variable impedances, respectively, through first and second logarithmic sequences of impedance values.

14. The method of claim 11 , wherein stepping the first and second variable impedances comprises:
stepping a series variable impedance and a shunt variable impedance in a first path between first and second ports of the switch.

15. The method of claim 11 , wherein stepping the first and second variable impedances, respectively, through first and second sequences of impedance values comprises:
stepping the first variable impedance through the first sequence of impedance values having a first range; and
stepping the second variable impedance through the second sequence of impedance values having a second range, the first and second ranges being different.

16. The method of claim 10 , the switch comprising a first series variable impedance and a first shunt variable impedance in a first path between first and third ports of the switch, a second series variable impedance and a second shunt variable impedance in a second path between second and third ports of the switch and a third shunt variable impedance coupled to the third port, wherein the method comprises:
maintaining impedances at the first, second and third ports of the switch during the first switch event by:
stepping at least two of: the first and second series variable impedances and first, second and third shunt variable impedances, through at least two sequences of impedance values during the first switch event.

17. The method of claim 11 , the first and second variable impedances respectively comprising first and second configurable transistor cells, wherein maintaining the impedance comprises:
selecting transistors in the first and second configurable transistor cells during the first switch event to generate the first and second sequences of impedance values.

18. The method of claim 10 , further comprising:
generating a sequence of control signals to step the first variable impedance through the first sequence of impedance values.

19. The method of claim 10 , further comprising:
calibrating the impedance of the switch during the first switch event by adjusting at least one time interval between steps in the first sequence of impedance values.

20. A method comprising:
determining first and second sequences of impedance values to step, respectively, first and second variable impedances in a switch during a switching event comprising a single state transition of the switch from a first state to a second state to maintain an impedance of the switch during the switching event.

Assignees

• Bawell Shawn
• Mourant Jean Marc
• Hubert Olivier
• Integrated Device Tech

Inventors

• Bawell Shawn
• Mourant Jean-Marc
• Hubert Olivier

Classifications

• H03H11/245 Primary

  using field-effect transistor · CPC title

• H03K17/56

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title

• H01C13/02

  Structural combinations of resistors · CPC title

• H01C1/16

  Resistor networks not otherwise provided for · CPC title

• H03K17/16

  Modifications for eliminating interference voltages or currents · CPC title